Issued Patents All Time
Showing 25 most recent of 48 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12423176 | Variable node data management for integrity check in memory systems | — | 2025-09-23 |
| 12362766 | Methods and systems for error-detecting during iterative decoding | — | 2025-07-15 |
| 12341530 | Check node updates in bit flipping decoders | Young Joon Ji | 2025-06-24 |
| 12316345 | Systems and methods for operating low-density parity-check bit-flipping decoder | — | 2025-05-27 |
| 12308855 | Methods and systems for error-detecting during iterative decoding | — | 2025-05-20 |
| 12301252 | Check node data compression in memory systems | — | 2025-05-13 |
| 12301253 | Check node data compression in memory systems | — | 2025-05-13 |
| 12231147 | Data structure reconfiguration for low density parity checks (LDPCs) in memory systems | — | 2025-02-18 |
| 12230346 | Cross-point memory read technique to mitigate drift errors | Hemant P. Rao, Raymond W. Zeng, Prashant S. Damle, Kiran Pangal, Mase J. Taub | 2025-02-18 |
| 12169435 | Dynamic self-correction of message reliability in LDPC codes | Debarnab Mitra, Ravi H. Motwani | 2024-12-17 |
| 12126361 | Techniques to improve latency of retry flow in memory controllers | Poovaiah M. Palangappa, Ravi H. Motwani | 2024-10-22 |
| 12038848 | Compression of logical-to-physical address indirection table on solid-state drives | — | 2024-07-16 |
| 11657889 | Error correction for dynamic data in a memory that is row addressable and column addressable | Jawad B. Khan, Richard Coulson, Ravi H. Motwani | 2023-05-23 |
| 11526279 | Technologies for performing column architecture-aware scrambling | Jawad B. Khan, Richard Coulson | 2022-12-13 |
| 11204718 | Apparatuses, systems, and methods to store pre-read data associated with a modify-write operation | Rajesh Sundaram, Muthukumar P. Swaminathan | 2021-12-21 |
| 11182240 | Techniques to improve error correction using an XOR rebuild scheme of multiple codewords and prevent miscorrection from read reference voltage shifts | Santhosh K. Vanaparthy, Ravi H. Motwani | 2021-11-23 |
| 11146289 | Techniques to use intrinsic information for a bit-flipping error correction control decoder | Aman Bhatia, Justin Kang, Poovaiah M. Palangappa, Santhosh K. Vanaparthy | 2021-10-12 |
| 11088707 | Low density parity check (LDPC) decoder architecture with check node storage (CNS) or bounded circulant | Poovaiah M. Palangappa | 2021-08-10 |
| 11086714 | Permutation of bit locations to reduce recurrence of bit error patterns in a memory device | Ravi H. Motwani | 2021-08-10 |
| 11063607 | Compressing error vectors for decoding logic to store compressed in a decoder memory used by the decoding logic | Poovaiah M. Palangappa | 2021-07-13 |
| 10839916 | One-sided soft reads | Pranav Kalavade, Ravi H. Motwani | 2020-11-17 |
| 10804935 | Techniques for reducing latency in the detection of uncorrectable codewords | — | 2020-10-13 |
| 10579473 | Mitigating silent data corruption in error control coding | Santhosh K. Vanaparthy, Ravi H. Motwani | 2020-03-03 |
| 10481974 | Apparatus, non-volatile memory storage device and method for detecting drift in non-volatile memory | Santhosh K. Vanaparthy, Ravi H. Motwani | 2019-11-19 |
| 10310989 | Time tracking with patrol scrub | Philip Hillier, Jeffrey W. Ryden, Muthukumar P. Swaminathan, Kunal A. Khochare, Richard P. Mangold +1 more | 2019-06-04 |