Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12176918 | Hybrid LDPC decoder with mixed precision components | Debarnab Mitra | 2024-12-24 |
| 12113547 | Application of low-density parity-check codes with codeword segmentation | Ravi H. Motwani | 2024-10-08 |
| 12032725 | Data scrambler for persistent memory | Ravi H. Motwani | 2024-07-09 |
| 11876622 | LDPC encoder and decoder for multi-mode higher speed passive optical networks | Rainer Strobel | 2024-01-16 |
| 11777530 | Methods and apparatuses for generating optimized LDPC codes | Ravi H. Motwani, Poovaiah M. Palangappa, Santosh Emmadi, Aman Bhatia | 2023-10-03 |
| 11515891 | Application of low-density parity-check codes with codeword segmentation | Ravi H. Motwani | 2022-11-29 |
| 11182240 | Techniques to improve error correction using an XOR rebuild scheme of multiple codewords and prevent miscorrection from read reference voltage shifts | Zion S. Kwok, Ravi H. Motwani | 2021-11-23 |
| 11159175 | Non-uniform iteration-dependent min-sum scaling factors for improved performance of spatially-coupled LDPC codes | Ravi H. Motwani | 2021-10-26 |
| 11146289 | Techniques to use intrinsic information for a bit-flipping error correction control decoder | Aman Bhatia, Zion S. Kwok, Justin Kang, Poovaiah M. Palangappa | 2021-10-12 |
| 10944428 | Device, system and method for determining bit reliability information | Ravi H. Motwani, Poovaiah M. Palangappa | 2021-03-09 |
| 10707901 | Die-wise residual bit error rate (RBER) estimation for memories | Poovaiah M. Palangappa, Ravi H. Motwani | 2020-07-07 |
| 10621035 | Techniques for correcting data errors in memory devices | Ravi H. Motwani | 2020-04-14 |
| 10579473 | Mitigating silent data corruption in error control coding | Ravi H. Motwani, Zion S. Kwok | 2020-03-03 |
| 10481974 | Apparatus, non-volatile memory storage device and method for detecting drift in non-volatile memory | Zion S. Kwok, Ravi H. Motwani | 2019-11-19 |