Issued Patents All Time
Showing 25 most recent of 38 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12040635 | System and method for dynamically balancing power from distributed power sources in a battery pack | Sunit Tyagi, Jitendra Apte, Anupam Hudait, Ranjith Nandakumar, Santhosha Gowda +2 more | 2024-07-16 |
| 11569668 | System and method for dynamic balancing power in a battery pack | Sunit Tyagi, Jitendra Apte, Anupam Hudait, Ranjith Nandakumar, Pooja Sharma +4 more | 2023-01-31 |
| 11183839 | DC-DC power conversion system | Jitendra Apte, Alok Srivastava, Sunit Tyagi, Dipti Kapadia, Vinod Kumar Singh +2 more | 2021-11-23 |
| 9739934 | Method for producing fibers having optical effect-producing nanostructures | Sunit Tyagi | 2017-08-22 |
| 9577548 | Power conversion for distributed DC source array | Sunit Tyagi | 2017-02-21 |
| 8940199 | Method for producing fibers having optical effect-producing nanostructures | Sunit Tyagi | 2015-01-27 |
| 8772865 | MOS transistor structure | Jeffrey Pearse, Prasad Venkatraman, James Sellers | 2014-07-08 |
| 8552560 | Alternate pad structures/passivation inegration schemes to reduce or eliminate IMC cracking in post wire bonded dies during Cu/Low-K BEOL processing | Dilip Vijay, Jayanthi Pallinti, Sey-Shing Sun, Hong Ying, Chiyi Kao | 2013-10-08 |
| 8552587 | Power conversion for distributed DC source array | Sunit Tyagi | 2013-10-08 |
| 8304314 | Method of forming an MOS transistor | Jeffrey Pearse, Prasad Venkatraman, James Sellers | 2012-11-06 |
| 8076779 | Reduction of macro level stresses in copper/low-K wafers | Sey-Shing Sun, Jayanthi Pallinti, Dilip Vijay, Hong Ying, Chiyi Kao +1 more | 2011-12-13 |
| 7955919 | Spacer-less transistor integration scheme for high-K gate dielectrics and small gate-to-gate spaces applicable to Si, SiGe and strained silicon schemes | David Pritchard, David T. Price | 2011-06-07 |
| 7915122 | Self-aligned cell integration scheme | Richard J. Carter, Shiqun Gu, Peter A. Burke, James R. B. Elmer, Sey-Shing Sun +2 more | 2011-03-29 |
| 7582566 | Method for redirecting void diffusion away from vias in an integrated circuit design | Derryl D. J. Allman, Charles E. May, Peter A. Burke, Byung Sung Kwak, Sey-Shing Sun +2 more | 2009-09-01 |
| 7531442 | Eliminate IMC cracking in post wirebonded dies: macro level stress reduction by modifying dielectric/metal film stack in be layers during Cu/Low-K processing | Jayanthi Pallinti, Dilip Vijay, Sey-Shing Sun, Hong Ying, Chiyi Kao +3 more | 2009-05-12 |
| 7456076 | Techniques for forming passive devices during semiconductor back-end processing | Santosh Menon | 2008-11-25 |
| 7436040 | Method and apparatus for diverting void diffusion in integrated circuit conductors | Derryl D. J. Allman, Charles E. May, Peter A. Burke, Byung Sung Kwak, Sey-Shing Sun +2 more | 2008-10-14 |
| 7402770 | Nano structure electrode design | Sey-Shing Sun, Peter A. Burke, Richard J. Carter | 2008-07-22 |
| 7384801 | Integrated circuit with inductor having horizontal magnetic flux lines | Jan Fure, Derryl D. J. Allman | 2008-06-10 |
| 7361965 | Method and apparatus for redirecting void diffusion away from vias in an integrated circuit design | Derryl D. J. Allman, Charles E. May, Peter A. Burke, Byung Sung Kwak, Sey-Shing Sun +2 more | 2008-04-22 |
| 7259083 | Local interconnect manufacturing process | Santosh Menon, David Pritchard | 2007-08-21 |
| 7253497 | Integrated circuit with inductor having horizontal magnetic flux lines | Jan Fure, Derryl D. J. Allman | 2007-08-07 |
| 7205673 | Reduce or eliminate IMC cracking in post wire bonded dies by doping aluminum used in bond pads during Cu/Low-k BEOL processing | Jayanthi Pallinti, Dilip Vijay, Sey-Shing Sun, Hong Ying, Chiyi Kao | 2007-04-17 |
| 7122436 | Techniques for forming passive devices during semiconductor back-end processing | Santosh Menon | 2006-10-17 |
| 6982206 | Mechanism for improving the structural integrity of low-k films | Michael Berman, Steven Reder | 2006-01-03 |