Issued Patents All Time
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12429627 | Surface modification control stations and methods in a globally distributed array for dynamically adjusting the atmospheric, terrestrial and oceanic properties | — | 2025-09-30 |
| 12040635 | System and method for dynamically balancing power from distributed power sources in a battery pack | Hemanshu Bhatt, Jitendra Apte, Anupam Hudait, Ranjith Nandakumar, Santhosha Gowda +2 more | 2024-07-16 |
| 11762126 | Surface modification control stations and methods in a globally distributed array for dynamically adjusting the atmospheric, terrestrial and oceanic properties | — | 2023-09-19 |
| 11569668 | System and method for dynamic balancing power in a battery pack | Jitendra Apte, Hemanshu Bhatt, Anupam Hudait, Ranjith Nandakumar, Pooja Sharma +4 more | 2023-01-31 |
| 11183839 | DC-DC power conversion system | Jitendra Apte, Alok Srivastava, Hemanshu Bhatt, Dipti Kapadia, Vinod Kumar Singh +2 more | 2021-11-23 |
| 9739934 | Method for producing fibers having optical effect-producing nanostructures | Hemanshu Bhatt | 2017-08-22 |
| 9577548 | Power conversion for distributed DC source array | Hemanshu Bhatt | 2017-02-21 |
| 8940199 | Method for producing fibers having optical effect-producing nanostructures | Hemanshu Bhatt | 2015-01-27 |
| 8552587 | Power conversion for distributed DC source array | Hemanshu Bhatt | 2013-10-08 |
| 7888710 | CMOS fabrication process utilizing special transistor orientation | Mark Armstrong, Gerhard Schrom, Paul Packan, Kelin J. Kuhn, Scott Thompson | 2011-02-15 |
| 7581154 | Method and apparatus to lower operating voltages for memory arrays using error correcting codes | Nivruti Rai, Anshumali Kumar, Edward A. Burton, Jeffrey L. Miller | 2009-08-25 |
| 7560780 | Active region spacer for semiconductor devices and method to form the same | Giuseppe Curello, Ian R. Post, Chia-Hong Jan, Mark Bohr | 2009-07-14 |
| 7473591 | Transistor with strain-inducing structure in channel | Stephen M. Cea, Ravindra Soman, Ramune Nagisetty, Sanjay Natarajan | 2009-01-06 |
| 7422950 | Strained silicon MOS device with box layer between the source and drain regions | Giuseppe Curello, Hemant Deshpande, Mark Bohr | 2008-09-09 |
| 7335959 | Device with stepped source/drain region profile | Giuseppe Curello, Bernhard Sell, Chris Auth | 2008-02-26 |
| 7312485 | CMOS fabrication process utilizing special transistor orientation | Mark Armstrong, Gerhard Schrom, Paul Packan, Kelin J. Kuhn, Scott Thompson | 2007-12-25 |
| 7019326 | Transistor with strain-inducing structure in channel | Stephen M. Cea, Ravindra Soman, Ramune Nagisetty, Sanjay Natarajan | 2006-03-28 |
| 6787440 | Method for making a semiconductor device having an ultra-thin high-k gate dielectric | Christopher Parker, Markus Kuhn, Ying Zhou, Scott A. Hareland, Suman Datta +4 more | 2004-09-07 |
| 6458667 | High power PMOS device | Shahriar Ahmed | 2002-10-01 |
| 6384457 | Asymmetric MOSFET devices | Shahriar Ahmed | 2002-05-07 |
| 6372583 | Process for making semiconductor device with epitaxially grown source and drain | — | 2002-04-16 |
| 6297104 | Methods to produce asymmetric MOSFET devices | Shahriar Ahmed | 2001-10-02 |
| 6249025 | Using epitaxially grown wells for reducing junction capacitances | — | 2001-06-19 |
| 6200879 | Using epitaxially grown wells for reducing junction capacitances | — | 2001-03-13 |
| 6177705 | High power PMOS device | Shahriar Ahmed | 2001-01-23 |