Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Sunit Tyagi — 26 Patents

Intel: 17 patents #2,442 of 30,777Top 8%
EDEmpire Technology Development: 2 patents #194 of 547Top 40%
Overall (All Time): #150,017 of 4,157,543Top 4%
26 Patents All Time
Sunit Tyagi has been granted 26 US patents while listed as an inventor at Intel. The first was granted in 1998 and the most recent in September 2025. Sunit Tyagi ranks #150,017 of 4,157,543 US inventors in our database (top 3.6%). Patent records list Sunit Tyagi in Kanchinakote, OR, IN.

Issued Patents All Time

Showing 1–25 of 26 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12429627 Surface modification control stations and methods in a globally distributed array for dynamically adjusting the atmospheric, terrestrial and oceanic properties 2025-09-30
12040635 System and method for dynamically balancing power from distributed power sources in a battery pack Hemanshu Bhatt, Jitendra Apte, Anupam Hudait, Ranjith Nandakumar, Santhosha Gowda +2 more 2024-07-16
11762126 Surface modification control stations and methods in a globally distributed array for dynamically adjusting the atmospheric, terrestrial and oceanic properties 2023-09-19
11569668 System and method for dynamic balancing power in a battery pack Jitendra Apte, Hemanshu Bhatt, Anupam Hudait, Ranjith Nandakumar, Pooja Sharma +4 more 2023-01-31
11183839 DC-DC power conversion system Jitendra Apte, Alok Srivastava, Hemanshu Bhatt, Dipti Kapadia, Vinod Kumar Singh +2 more 2021-11-23
9739934 Method for producing fibers having optical effect-producing nanostructures Hemanshu Bhatt 2017-08-22
9577548 Power conversion for distributed DC source array Hemanshu Bhatt 2017-02-21
8940199 Method for producing fibers having optical effect-producing nanostructures Hemanshu Bhatt 2015-01-27
8552587 Power conversion for distributed DC source array Hemanshu Bhatt 2013-10-08
7888710 CMOS fabrication process utilizing special transistor orientation Mark Armstrong, Gerhard Schrom, Paul Packan, Kelin J. Kuhn, Scott Thompson 2011-02-15 $18,725,000
7581154 Method and apparatus to lower operating voltages for memory arrays using error correcting codes Nivruti Rai, Anshumali Kumar, Edward A. Burton, Jeffrey L. Miller 2009-08-25 $20,594,000
7560780 Active region spacer for semiconductor devices and method to form the same Giuseppe Curello, Ian R. Post, Chia-Hong Jan, Mark Bohr 2009-07-14 $21,399,000
7473591 Transistor with strain-inducing structure in channel Stephen M. Cea, Ravindra Soman, Ramune Nagisetty, Sanjay Natarajan 2009-01-06 $21,219,000
7422950 Strained silicon MOS device with box layer between the source and drain regions Giuseppe Curello, Hemant Deshpande, Mark Bohr 2008-09-09 $18,766,000
7335959 Device with stepped source/drain region profile Giuseppe Curello, Bernhard Sell, Chris Auth 2008-02-26 $16,748,000
7312485 CMOS fabrication process utilizing special transistor orientation Mark Armstrong, Gerhard Schrom, Paul Packan, Kelin J. Kuhn, Scott Thompson 2007-12-25
7019326 Transistor with strain-inducing structure in channel Stephen M. Cea, Ravindra Soman, Ramune Nagisetty, Sanjay Natarajan 2006-03-28 $11,012,000
6787440 Method for making a semiconductor device having an ultra-thin high-k gate dielectric Christopher Parker, Markus Kuhn, Ying Zhou, Scott A. Hareland, Suman Datta +4 more 2004-09-07 $21,424,000
6458667 High power PMOS device Shahriar Ahmed 2002-10-01 $50,099,000
6384457 Asymmetric MOSFET devices Shahriar Ahmed 2002-05-07 $68,605,000
6372583 Process for making semiconductor device with epitaxially grown source and drain 2002-04-16 $77,675,000
6297104 Methods to produce asymmetric MOSFET devices Shahriar Ahmed 2001-10-02 $98,303,000
6249025 Using epitaxially grown wells for reducing junction capacitances 2001-06-19 $181,106,000
6200879 Using epitaxially grown wells for reducing junction capacitances 2001-03-13 $189,401,000
6177705 High power PMOS device Shahriar Ahmed 2001-01-23 $255,018,000