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USPTO Patent Rankings Data through Dec 31, 2025
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Giuseppe Curello — 16 Patents

Intel: 14 patents #2,935 of 30,777Top 10%
Infineon Technologies Ag: 2 patents #3,286 of 7,486Top 45%
Overall (All Time): #284,196 of 4,157,543Top 7%
16 Patents All Time
Giuseppe Curello has been granted 16 US patents while listed as an inventor at Intel. The first was granted in 2003 and the most recent in June 2019. Giuseppe Curello ranks #284,196 of 4,157,543 US inventors in our database (top 6.8%). Patent records list Giuseppe Curello in Munich, OR, DE.

Issued Patents All Time

Showing 1–16 of 16 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
10332871 Area-efficient and robust electrostatic discharge circuit Christian Russ, Tomasz Biedrzycki, Franz Kuttner, Luis-Felipe Giles, Bernhard Stein 2019-06-25
8741720 Penetrating implant for forming a semiconductor device Ian R. Post, Nick Lindert, Walid M. Hafez, Chia-Hong Jan, Mark Bohr 2014-06-03 $12,928,000
8426927 Penetrating implant for forming a semiconductor device Ian R. Post, Nick Lindert, Walid M. Hafez, Chia-Hong Jan, Mark Bohr 2013-04-23 $13,399,000
8174060 Selective spacer formation on transistors of different classes on the same device Ian R. Post, Chia-Hong Jan, Mark Bohr 2012-05-08 $29,842,000
8154067 Selective spacer formation on transistors of different classes on the same device Ian R. Post, Chia-Hong Jan, Mark Bohr 2012-04-10 $33,757,000
7943468 Penetrating implant for forming a semiconductor device Ian R. Post, Nick Lindert, Walid M. Hafez, Chia-Hong Jan, Mark Bohr 2011-05-17 $24,931,000
7560780 Active region spacer for semiconductor devices and method to form the same Ian R. Post, Chia-Hong Jan, Sunit Tyagi, Mark Bohr 2009-07-14 $21,399,000
7541239 Selective spacer formation on transistors of different classes on the same device Ian R. Post, Chia-Hong Jan, Mark Bohr 2009-06-02 $16,449,000
7482670 Enhancing strained device performance by use of multi narrow section layout Thomas Hoffmann, Mark Armstrong 2009-01-27 $21,790,000
7422950 Strained silicon MOS device with box layer between the source and drain regions Hemant Deshpande, Sunit Tyagi, Mark Bohr 2008-09-09 $18,766,000
7335959 Device with stepped source/drain region profile Bernhard Sell, Sunit Tyagi, Chris Auth 2008-02-26 $16,748,000
7129533 High concentration indium fluorine retrograde wells Cory E. Weber, Mark Armstrong, Stephen M. Cea, Sing-Chung Hu, Aaron D. Lilak +1 more 2006-10-31 $18,482,000
7101765 Enhancing strained device performance by use of multi narrow section layout Thomas Hoffmann, Mark Armstrong 2006-09-05 $13,820,000
7078325 Process for producing a doped semiconductor substrate Jurgen Faul 2006-07-18 $183,000
6838329 High concentration indium fluorine retrograde wells Cory E. Weber, Mark Armstrong, Stephen M. Cea, Sing-Chung Hu, Aaron D. Lilak +1 more 2005-01-04 $23,080,000
6503844 Notched gate configuration for high performance integrated circuits 2003-01-07 $107,000