IP

Ian R. Post

IN Intel: 18 patents #2,286 of 30,777Top 8%
RTX (Raytheon): 3 patents #3,861 of 15,912Top 25%
SO Sony: 2 patents #12,963 of 25,231Top 55%
Overall (All Time): #170,448 of 4,157,543Top 5%
24
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12021141 Multi-threshold voltage devices and associated techniques and configurations Joseph M. Steigerwald, Tahir Ghani, Jenny Hu 2024-06-25
11437511 Multi-threshold voltage devices and associated techniques and configurations Joseph M. Steigerwald, Tahir Ghani, Jenny Hu 2022-09-06
10573747 Multi-threshold voltage devices and associated techniques and configurations Joseph M. Steigerwald, Tahir Ghani, Jenny Hu 2020-02-25
9761713 Multi-threshold voltage devices and associated techniques and configurations Joseph M. Steigerwald, Tahir Ghani, Jenny Hu 2017-09-12
9219155 Multi-threshold voltage devices and associated techniques and configurations Joseph M. Steigerwald, Tahir Ghani, Jenny Hu 2015-12-22
8741720 Penetrating implant for forming a semiconductor device Giuseppe Curello, Nick Lindert, Walid M. Hafez, Chia-Hong Jan, Mark Bohr 2014-06-03
8426927 Penetrating implant for forming a semiconductor device Giuseppe Curello, Nick Lindert, Walid M. Hafez, Chia-Hong Jan, Mark Bohr 2013-04-23
8174060 Selective spacer formation on transistors of different classes on the same device Giuseppe Curello, Chia-Hong Jan, Mark Bohr 2012-05-08
8154067 Selective spacer formation on transistors of different classes on the same device Giuseppe Curello, Chia-Hong Jan, Mark Bohr 2012-04-10
7943468 Penetrating implant for forming a semiconductor device Giuseppe Curello, Nick Lindert, Walid M. Hafez, Chia-Hong Jan, Mark Bohr 2011-05-17
7560780 Active region spacer for semiconductor devices and method to form the same Giuseppe Curello, Chia-Hong Jan, Sunit Tyagi, Mark Bohr 2009-07-14
7541239 Selective spacer formation on transistors of different classes on the same device Giuseppe Curello, Chia-Hong Jan, Mark Bohr 2009-06-02
7226843 Indium-boron dual halo MOSFET Cory E. Weber, Gerhard Schrom, Mark Stettler 2007-06-05
6979609 Method of fabricating MOSFET transistors with multiple threshold voltages by halo compensation and masks Kaizad Mistry 2005-12-27
6803285 Method of fabricating dual threshold voltage n-channel and p-channel mosfets with a single extra masked implant operation Kaizad Mistry 2004-10-12
6717221 Method of fabricating MOSFET transistors with multiple threshold voltages by halo compensation and masks Kaizad Mistry 2004-04-06
6693331 Method of fabricating dual threshold voltage n-channel and p-channel MOSFETS with a single extra masked implant operation Kaizad Mistry 2004-02-17
6627506 Thin tensile layers in shallow trench isolation and method of making same Kelin J. Kuhn 2003-09-30
6586294 Method of fabricating MOSFET transistors with multiple threshold voltages by halo compensation and masks Kaizad Mistry 2003-07-01
6368931 Thin tensile layers in shallow trench isolation and method of making same Kelin J. Kuhn 2002-04-09
5670394 Method of making bipolar transistor having amorphous silicon contact as emitter diffusion source Rick C. Jerome 1997-09-23
5565370 Method of enhancing the current gain of bipolar junction transistors Rick C. Jerome, Gary M. Wodek 1996-10-15
5561073 Method of fabricating an isolation trench for analog bipolar devices in harsh environments Rick C. Jerome 1996-10-01
5420050 Method of enhancing the current gain of bipolar junction transistors Rick C. Jerome, Gary M. Wodek 1995-05-30