Issued Patents All Time
Showing 25 most recent of 147 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12389626 | High-voltage transistor with self-aligned isolation | Walid M. Hafez | 2025-08-12 |
| 12317585 | Adjacent gate-all-around integrated circuit structures having non-merged epitaxial source or drain regions | Sairam Subramanian, Walid M. Hafez, Hsu-Yu Chang, Tanuj Trivedi | 2025-05-27 |
| 12191207 | Non-planar I/O and logic semiconductor devices having different workfunction on common substrate | Roman W. Olac-Vaw, Walid M. Hafez, Pei-Chi Liu | 2025-01-07 |
| 12136628 | High voltage three-dimensional devices having dielectric liners | Walid M. Hafez, Jeng-Ya David Yeh, Curtis Tsai, Joodong Park, Gopinath Bhimarasetti | 2024-11-05 |
| 11967615 | Dual threshold voltage (VT) channel devices and their methods of fabrication | Hsu-Yu Chang, Neville L. Dias, Walid M. Hafez, Roman W. Olac-Vaw, Chen-Guan Lee | 2024-04-23 |
| 11881486 | High voltage three-dimensional devices having dielectric liners | Walid M. Hafez, Jeng-Ya David Yeh, Curtis Tsai, Joodong Park, Gopinath Bhimarasetti | 2024-01-23 |
| 11830818 | Semiconductor device having metal interconnects with different thicknesses | Kinyip Phoa, Jui-Yen Lin, Nidhi Nidhi | 2023-11-28 |
| 11823954 | Non-planar I/O and logic semiconductor devices having different workfunction on common substrate | Roman W. Olac-Vaw, Walid M. Hafez, Pei-Chi Liu | 2023-11-21 |
| 11824002 | Variable pitch and stack height for high performance interconnects | En-Shao Liu, Joodong Park, Chen-Guan Lee, Walid M. Hafez, Jiansheng Xu | 2023-11-21 |
| 11764260 | Dielectric and isolation lower fin material for fin-based electronics | Walid M. Hafez | 2023-09-19 |
| 11737362 | Harvesting energy in an integrated circuit using the seebeck effect | Kinyip Phoa, Jui-Yen Lin, Nidhi Nidhi | 2023-08-22 |
| 11695008 | Methods of integrating multiple gate dielectric transistors on a tri-gate (FINFET) process | Curtis Tsai, Jeng-Ya David Yeh, Joodong Park, Walid M. Hafez | 2023-07-04 |
| 11688792 | Dual self-aligned gate endcap (SAGE) architectures | Sairam Subramanian, Walid M. Hafez, Sridhar Govindaraju, Mark Liu, Szuya S. Liao +2 more | 2023-06-27 |
| 11610917 | High voltage three-dimensional devices having dielectric liners | Walid M. Hafez, Jeng-Ya David Yeh, Curtis Tsai, Joodong Park, Gopinath Bhimarasetti | 2023-03-21 |
| 11605632 | Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls | Walid M. Hafez, Sridhar Govindaraju, Mark Liu, Szuya S. Liao, Nick Lindert +2 more | 2023-03-14 |
| 11563000 | Gate endcap architectures having relatively short vertical stack | Sairam Subramanian, Walid M. Hafez, Hsu-Yu Chang | 2023-01-24 |
| 11562999 | Cost effective precision resistor using blocked DEPOP method in self-aligned gate endcap (SAGE) architecture | Roman W. Olac-Vaw, Nick Lindert, Walid M. Hafez | 2023-01-24 |
| 11335601 | Non-planar I/O and logic semiconductor devices having different workfunction on common substrate | Roman W. Olac-Vaw, Walid M. Hafez, Pei-Chi Liu | 2022-05-17 |
| 11329138 | Self-aligned gate endcap (SAGE) architecture having endcap plugs | Sairam Subramanian, Christopher KENYON, Sridhar Govindaraju, Mark Liu, Szuya S. Liao +1 more | 2022-05-10 |
| 11276760 | Non-planar semiconductor device having omega-fin with doped sub-fin region and method to fabricate same | Gopinath Bhimarasetti, Walid M. Hafez, Joodong Park, Weimin Han, Raymond E. Cotner | 2022-03-15 |
| 11264329 | Semiconductor device having metal interconnects with different thicknesses | Kinyip Phoa, Jui-Yen Lin, Nidhi Nidhi | 2022-03-01 |
| 11251201 | High voltage three-dimensional devices having dielectric liners | Walid M. Hafez, Jeng-Ya David Yeh, Curtis Tsai, Joodong Park, Gopinath Bhimarasetti | 2022-02-15 |
| 11217582 | Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls | Walid M. Hafez, Sridhar Govindaraju, Mark Liu, Szuya S. Liao, Nick Lindert +2 more | 2022-01-04 |
| 11205708 | Dual self-aligned gate endcap (SAGE) architectures | Sairam Subramanian, Walid M. Hafez, Sridhar Govindaraju, Mark Liu, Szuya S. Liao +2 more | 2021-12-21 |
| 11139370 | Dielectric and isolation lower fin material for fin-based electronics | Walid M. Hafez | 2021-10-05 |