Issued Patents All Time
Showing 25 most recent of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12136628 | High voltage three-dimensional devices having dielectric liners | Walid M. Hafez, Jeng-Ya David Yeh, Curtis Tsai, Chia-Hong Jan, Gopinath Bhimarasetti | 2024-11-05 |
| 11881486 | High voltage three-dimensional devices having dielectric liners | Walid M. Hafez, Jeng-Ya David Yeh, Curtis Tsai, Chia-Hong Jan, Gopinath Bhimarasetti | 2024-01-23 |
| 11824002 | Variable pitch and stack height for high performance interconnects | En-Shao Liu, Chen-Guan Lee, Walid M. Hafez, Chia-Hong Jan, Jiansheng Xu | 2023-11-21 |
| 11695008 | Methods of integrating multiple gate dielectric transistors on a tri-gate (FINFET) process | Curtis Tsai, Chia-Hong Jan, Jeng-Ya David Yeh, Walid M. Hafez | 2023-07-04 |
| 11610917 | High voltage three-dimensional devices having dielectric liners | Walid M. Hafez, Jeng-Ya David Yeh, Curtis Tsai, Chia-Hong Jan, Gopinath Bhimarasetti | 2023-03-21 |
| 11276760 | Non-planar semiconductor device having omega-fin with doped sub-fin region and method to fabricate same | Gopinath Bhimarasetti, Walid M. Hafez, Weimin Han, Raymond E. Cotner, Chia-Hong Jan | 2022-03-15 |
| 11251201 | High voltage three-dimensional devices having dielectric liners | Walid M. Hafez, Jeng-Ya David Yeh, Curtis Tsai, Chia-Hong Jan, Gopinath Bhimarasetti | 2022-02-15 |
| 11121040 | Multi voltage threshold transistors through process and design-induced multiple work functions | Chen-Guan Lee, Everett S. Cassidy-Comfort, Walid M. Hafez, Chia-Hong Jan, Rahul Ramaswamy +2 more | 2021-09-14 |
| 11114538 | Transistor with an airgap spacer adjacent to a transistor gate | Chen-Guan Lee, En-Shao Liu, Everett S. Cassidy-Comfort, Walid M. Hafez, Chia-Hong Jan | 2021-09-07 |
| 11063137 | Asymmetric spacer for low capacitance applications | Jui-Yen Lin, Chen-Guan Lee, Walid M. Hafez, Kun-Huan Shih | 2021-07-13 |
| 10923574 | Transistor with inner-gate spacer | En-Shao Liu, Chen-Guan Lee, Jui-Yen Lin, Chia-Hong Jan | 2021-02-16 |
| 10892261 | Metal resistor and self-aligned gate edge (SAGE) architecture having a metal resistor | Walid M. Hafez, Roman W. Olac-Vaw, Chen-Guan Lee, Chia-Hong Jan | 2021-01-12 |
| 10847544 | High voltage three-dimensional devices having dielectric liners | Walid M. Hafez, Jeng-Ya David Yeh, Curtis Tsai, Chia-Hong Jan, Gopinath Bhimarasetti | 2020-11-24 |
| 10784378 | Ultra-scaled fin pitch having dual gate dielectrics | Walid M. Hafez, Roman W. Olac-Vaw, Chen-Guan Lee, Chia-Hong Jan, Everett S. Cassidy-Comfort | 2020-09-22 |
| 10692888 | High voltage three-dimensional devices having dielectric liners | Walid M. Hafez, Jeng-Ya David Yeh, Curtis Tsai, Chia-Hong Jan, Gopinath Bhimarasetti | 2020-06-23 |
| 10658361 | Methods of integrating multiple gate dielectric transistors on a tri-gate (FINFET) process | Curtis Tsai, Chia-Hong Jan, Jeng-Ya David Yeh, Walid M. Hafez | 2020-05-19 |
| 10559688 | Transistor with thermal performance boost | Chen-Guan Lee, Walid M. Hafez, Chia-Hong Jan, Hsu-Yu Chang | 2020-02-11 |
| 10535747 | Transistor with dual-gate spacer | En-Shao Liu, Chen-Guan Lee, Chia-Hong Jan | 2020-01-14 |
| 10431661 | Transistor with inner-gate spacer | En-Shao Liu, Chen-Guan Lee, Jui-Yen Lin, Chia-Hong Jan | 2019-10-01 |
| 10355093 | Non-planar semiconductor device having omega-fin with doped sub-fin region and method to fabricate same | Gopinath Bhimarasetti, Walid M. Hafez, Weimin Han, Raymond E. Cotner, Chia-Hong Jan | 2019-07-16 |
| 10340220 | Compound lateral resistor structures for integrated circuitry | Chen-Guan Lee, Vadym Kapinus, Pei-Chi Liu, Walid M. Hafez, Chia-Hong Jan | 2019-07-02 |
| 10304681 | Dual height glass for finFET doping | Chen-Guan Lee, Lu Yang, Chia-Hong Jan | 2019-05-28 |
| 10263112 | Vertical non-planar semiconductor device for system-on-chip (SoC) applications | Chia-Hong Jan, Walid M. Hafez, Curtis Tsai, Jeng-Ya David Yeh | 2019-04-16 |
| 10204999 | Transistor with airgap spacer | Chen-Guan Lee, En-Shao Liu, Everett S. Cassidy-Comfort, Walid M. Hafez, Chia-Hong Jan | 2019-02-12 |
| 10096599 | Methods of integrating multiple gate dielectric transistors on a tri-gate (finFET) process | Curtis Tsai, Chia-Hong Jan, Jeng-Ya David Yeh, Walid M. Hafez | 2018-10-09 |