Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12341061 | Bottom-up fill dielectric materials for semiconductor structure fabrication and their methods of fabrication | Florian Gstrein, Rami Hourani, James M. Blackwell | 2025-06-24 |
| 12136628 | High voltage three-dimensional devices having dielectric liners | Walid M. Hafez, Jeng-Ya David Yeh, Curtis Tsai, Joodong Park, Chia-Hong Jan | 2024-11-05 |
| 11881486 | High voltage three-dimensional devices having dielectric liners | Walid M. Hafez, Jeng-Ya David Yeh, Curtis Tsai, Joodong Park, Chia-Hong Jan | 2024-01-23 |
| 11664274 | Method to repair edge placement errors in a semiconductor device | Charles H. Wallace, Mohit K. HARAN | 2023-05-30 |
| 11610917 | High voltage three-dimensional devices having dielectric liners | Walid M. Hafez, Jeng-Ya David Yeh, Curtis Tsai, Joodong Park, Chia-Hong Jan | 2023-03-21 |
| 11456372 | Multi-height finfet device by selective oxidation | Seiyon Kim, Rafael Rios, Jack T. Kavalieros, Tahir Ghani, Anand S. Murthy +1 more | 2022-09-27 |
| 11276760 | Non-planar semiconductor device having omega-fin with doped sub-fin region and method to fabricate same | Walid M. Hafez, Joodong Park, Weimin Han, Raymond E. Cotner, Chia-Hong Jan | 2022-03-15 |
| 11251201 | High voltage three-dimensional devices having dielectric liners | Walid M. Hafez, Jeng-Ya David Yeh, Curtis Tsai, Joodong Park, Chia-Hong Jan | 2022-02-15 |
| 11232980 | Bottom-up fill dielectric materials for semiconductor structure fabrication and their methods of fabrication | Florian Gstrein, Rami Hourani, James M. Blackwell | 2022-01-25 |
| 11227863 | Gate isolation in non-planar transistors | Leonard P. GULER, Vyom Sharma, Walid M. Hafez, Christopher P. Auth | 2022-01-18 |
| 10879241 | Techniques for controlling transistor sub-fin leakage | Glenn A. Glass, Prashant Majhi, Anand S. Murthy, Tahir Ghani, Daniel B. Aubertine +2 more | 2020-12-29 |
| 10847544 | High voltage three-dimensional devices having dielectric liners | Walid M. Hafez, Jeng-Ya David Yeh, Curtis Tsai, Joodong Park, Chia-Hong Jan | 2020-11-24 |
| 10797047 | Gate isolation in non-planar transistors | Leonard P. GULER, Vyom Sharma, Walid M. Hafez, Christopher P. Auth | 2020-10-06 |
| 10692888 | High voltage three-dimensional devices having dielectric liners | Walid M. Hafez, Jeng-Ya David Yeh, Curtis Tsai, Joodong Park, Chia-Hong Jan | 2020-06-23 |
| 10529660 | Pore-filled dielectric materials for semiconductor structure fabrication and their methods of fabrication | Jessica M. Torres, Jeffery D. Bielefeld, Mauro J. Kobrinsky, Christopher J. Jezewski | 2020-01-07 |
| 10424580 | Semiconductor devices having modulated nanowire counts | Annalisa Cappellani, Kelin J. Kuhn, Rafael Rios, Tahir Ghani, Seiyon Kim | 2019-09-24 |
| 10355093 | Non-planar semiconductor device having omega-fin with doped sub-fin region and method to fabricate same | Walid M. Hafez, Joodong Park, Weimin Han, Raymond E. Cotner, Chia-Hong Jan | 2019-07-16 |
| 9972642 | High voltage three-dimensional devices having dielectric liners | Walid M. Hafez, Jeng-Ya David Yeh, Curtis Tsai, Joodong Park, Chia-Hong Jan | 2018-05-15 |
| 9806095 | High voltage three-dimensional devices having dielectric liners | Walid M. Hafez, Jeng-Ya David Yeh, Curtis Tsai, Joodong Park, Chia-Hong Jan | 2017-10-31 |
| 9741721 | Low leakage non-planar access transistor for embedded dynamic random access memory (eDRAM) | Joodong Park, Rahul Ramaswamy, Chia-Hong Jan, Walid M. Hafez, Jeng-Ya David Yeh +1 more | 2017-08-22 |
| 9570467 | High voltage three-dimensional devices having dielectric liners | Walid M. Hafez, Jeng-Ya David Yeh, Curtis Tsai, Joodong Park, Chia-Hong Jan | 2017-02-14 |
| 8981481 | High voltage three-dimensional devices having dielectric liners | Walid M. Hafez, Jeng-Ya David Yeh, Curtis Tsai, Joodong Park, Chia-Hong Jan | 2015-03-17 |
| 7597941 | Tubular carbon nano/micro structures and method of making same | Mahendra Kumar Sunkara | 2009-10-06 |