Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
CJ

Christopher J. Jezewski — 76 Patents

Intel: 70 patents #390 of 30,777Top 2%
TRTahoe Research: 3 patents #2 of 215Top 1%
ELEaton Intelligent Power Limited: 2 patents #743 of 2,212Top 35%
Portland, OR: #188 of 9,213 inventorsTop 3%
Oregon: #359 of 28,073 inventorsTop 2%
Overall (All Time): #24,882 of 4,157,543Top 1%
76 Patents All Time
Christopher J. Jezewski has been granted 76 US patents while listed as an inventor at Intel. The first was granted in 2003 and the most recent in November 2025. Christopher J. Jezewski ranks #24,882 of 4,157,543 US inventors in our database (top 0.60%). Patent records list Christopher J. Jezewski in Portland, OR, US.

Issued Patents All Time

Showing 1–25 of 76 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12482744 Subtractively patterned interconnect structures for integrated circuits Keh-I Lin, Noriyuki Sato, Tristan A. Tronic, Michael Christenson, Jianxin Chen +10 more 2025-11-25
12394716 Integrated circuit interconnect structures with graphene cap Carl Naylor, Jasmeet S. Chawla, Matthew V. Metz, Sean King, Ramanan V. Chebiam +5 more 2025-08-19
12354956 Cobalt based interconnects and methods of fabrication thereof Tejaswi K. Indukuri, Ramanan V. Chebiam, Colin T. Carver 2025-07-08
12328927 Low resistance and reduced reactivity approaches for fabricating contacts and the resulting structures Gilbert Dewey, Nazila Haratipour, Siddharth Chouksey, Arnab Sen Gupta, I-Cheng Tung +2 more 2025-06-10
12322699 Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches Jasmeet S. Chawla 2025-06-03
12261114 Metallization stacks with self-aligned staggered metal lines Elijah V. Karpov, Manish Chandhok, Nafees Kabir, Matthew V. Metz 2025-03-25
12211794 Integrated circuits and methods for forming thin film crystal layers Carl Naylor, Ashish Agrawal, Kevin Lin, Abhishek A. Sharma, Mauro J. Kobrinsky +1 more 2025-01-28
12170319 Dual contact process with stacked metal layers Kevin T. Cook, Anand S. Murthy, Gilbert Dewey, Nazila Haratipour, Ralph T. Troeger +1 more 2024-12-17 $33,648,000
12165917 Integrated circuit interconnect structures with ultra-thin metal chalcogenide barrier materials Carl Naylor 2024-12-10 $13,394,000
12107085 Interconnect techniques for electrically connecting source/drain regions of stacked transistors Aaron D. Lilak, Gilbert Dewey, Cheng-Ying Huang, Ehren Mannebach, Rishabh Mehandru +4 more 2024-10-01 $20,560,000
12107170 Transistor channel passivation with 2D crystalline material Carl Naylor, Abhishek A. Sharma, Mauro J. Kobrinsky, Urusa Alaan, Justin R. Weber 2024-10-01 $20,560,000
12033896 Isolation wall stressor structures to improve channel stress and their methods of fabrication Aaron D. Lilak, Willy Rachmady, Rishabh Mehandru, Gilbert Dewey, Anh Phan 2024-07-09 $24,938,000
12027458 Subtractively patterned interconnect structures for integrated circuits Kevin Lin, Noriyuki Sato, Tristan A. Tronic, Michael Christenson, Jiun-Ruey Chen +10 more 2024-07-02 $27,114,000
11888034 Transistors with metal chalcogenide channel materials Abhishek A. Sharma, Ashish Agarwal, Urusa Alaan, Kevin Lin, Carl Naylor 2024-01-30 $30,721,000
11869894 Metallization structures for stacked device connectivity and their methods of fabrication Aaron D. Lilak, Anh Phan, Patrick Morrow, Willy Rachmady, Gilbert Dewey +6 more 2024-01-09 $30,329,000
11862563 Cobalt based interconnects and methods of fabrication thereof Tejaswi K. Indukuri, Ramanan V. Chebiam, Colin T. Carver 2024-01-02
11830788 Integrated circuits and methods for forming integrated circuits Carl Naylor, Ashish Agrawal, Urusa Alaan, Mauro J. Kobrinsky, Kevin Lin +1 more 2023-11-28 $31,872,000
11830768 Integrated circuits with line breaks and line bridges within a single interconnect level Kevin Lin 2023-11-28 $31,872,000
11749560 Cladded metal interconnects Thomas Marieb, Zhiyong Ma, Miriam Reshotko, Flavio Griggio, Rahim Kasim +1 more 2023-09-05 $19,899,000
11742346 Interconnect techniques for electrically connecting source/drain regions of stacked transistors Aaron D. Lilak, Gilbert Dewey, Cheng-Ying Huang, Ehren Mannebach, Rishabh Mehandru +4 more 2023-08-29 $19,273,000
11670588 Selectable vias for back end of line interconnects Ashish Agrawal, Kevin Lin, Abhishek A. Sharma, Carl Naylor, Urusa Alaan 2023-06-06 $21,341,000
11664305 Staggered lines for interconnect performance improvement and processes for forming such Kevin Lin, Manish Chandhok, Miriam Reshotko, Eungnak Han, Gurpreet Singh +2 more 2023-05-30 $16,378,000
11652067 Methods of forming substrate interconnect structures for enhanced thin seed conduction Radek P. Chalupa, Flavio Griggio, Inane Meric, Jiun-Chan Yang 2023-05-16 $11,130,000
11637185 Contact stacks to reduce hydrogen in semiconductor devices Justin R. Weber, Harold W. Kennel, Abhishek A. Sharma, Matthew V. Metz, Tahir Ghani +4 more 2023-04-25 $19,274,000
11626451 Magnetic memory device with ruthenium diffusion barrier Emily Walker, Carl Naylor, Kaan Oguz, Kevin Lin, Tanay Gosavi +6 more 2023-04-11 $27,486,000