Issued Patents All Time
Showing 25 most recent of 482 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12426360 | Wrap-around trench contact structure and methods of fabrication | Joseph M. Steigerwald, Oleg Golonzka | 2025-09-23 |
| 12426342 | Low germanium, high boron silicon rich capping layer for PMOS contact resistance thermal stability | Debaleena Nandi, Cory Bomberger, Gilbert Dewey, Anand S. Murthy, Mauro J. Kobrinsky +6 more | 2025-09-23 |
| 12426230 | Fin cut and fin trim isolation for advanced integrated circuit structure fabrication | Byron Ho, Curtis W. Ward, Michael L. Hattendorf, Christopher P. Auth | 2025-09-23 |
| 12426316 | Method of fabricating integrated circuits with fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric material | Leonard P. GULER, Nick Lindert, Biswajeet Guha, Swaminathan Sivakumar | 2025-09-23 |
| 12426247 | Capacitor connections in dielectric layers | Travis W. Lajoie, Abhishek A. Sharma, Van H. Le, Chieh-Jen Ku, Pei-Hua Wang +13 more | 2025-09-23 |
| 12419091 | Source electrode and drain electrode protection for nanowire transistors | Karthik Jambunathan, Biswajeet Guha, Anand S. Murthy | 2025-09-16 |
| 12419085 | Integrated circuit structures having backside gate tie-down | Leonard P. GULER, Mauro J. Kobrinsky, Mohit K. HARAN, Marni Nabors, Charles H. Wallace +2 more | 2025-09-16 |
| 12414327 | Lateral confinement of source drain epitaxial growth in non-planar transistor for cell height scaling | Nitesh Kumar, Mohammed Hasan, Vivek Thirtha, Nikhil MEHTA | 2025-09-09 |
| 12408422 | Integrated circuit structures with backside gate cut or trench contact cut | Leonard P. GULER, Charles H. Wallace | 2025-09-02 |
| 12405526 | Extreme ultraviolet lithography patterning with assist features | Leonard P. GULER, Charles H. Wallace, Hossam A. Abdallah, Dario Farias, Tsuan-Chung CHANG +5 more | 2025-09-02 |
| 12402349 | Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact | Biswajeet Guha, William Hsu, Chung-Hsun Lin, Kinyip Phoa, Oleg Golonzka +5 more | 2025-08-26 |
| 12382706 | Self-aligned gate endcap (SAGE) architectures with gate-all-around devices | Biswajeet Guha, William Hsu, Leonard P. GULER, Dax M. Crum | 2025-08-05 |
| 12382721 | Integrated circuit structures having cut metal gates with dielectric spacer fill | Leonard P. GULER, Chanaka D. Munasinghe, Makram ABD EL QADER, Marie T. Conte, Saurabh Morarka +5 more | 2025-08-05 |
| 12369393 | Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up approach | Dax M. Crum, Biswajeet Guha, Leonard P. GULER | 2025-07-22 |
| 12369392 | Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates | Leonard P. GULER, Michael K. Harper, William Hsu, Biswajeet Guha, Niels Zussblatt +6 more | 2025-07-22 |
| 12364002 | Integrated circuit structures having metal gates with tapered plugs | Mohammad HASAN, Biswajeet Guha, Oleg Golonzka, Leonard P. GULER, Leah Shoer +2 more | 2025-07-15 |
| 12364001 | Integrated circuit structures with backside gate partial cut or trench contact partial cut | Leonard P. GULER, Mohammad HASAN, Charles H. Wallace | 2025-07-15 |
| 12363967 | Integration methods to fabricate internal spacers for nanowire devices | Seiyon Kim, Kelin J. Kuhn, Anand S. Murthy, Mark Armstrong, Rafael Rios +2 more | 2025-07-15 |
| 12349420 | Device, method and system to provide a stressed channel of a transistor | Rishabh Mehandru, Stephen M. Cea, Anand S. Murthy | 2025-07-01 |
| 12349416 | Transistor structures with a metal oxide contact buffer and a method of fabricating the transistor structures | Gilbert Dewey, Abhishek A. Sharma, Van H. Le, Jack T. Kavalieros, Shriram Shivaraman +4 more | 2025-07-01 |
| 12342612 | Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions | Leonard P. GULER, Biswajeet Guha, Swaminathan Sivakumar | 2025-06-24 |
| 12336278 | Gate-all-around integrated circuit structures having high mobility | Roza Kotlyar, Rishabh Mehandru, Stephen M. Cea, Biswajeet Guha, Dax M. Crum | 2025-06-17 |
| 12328920 | Nanoribbon sub-fin isolation by backside Si substrate removal etch selective to source and drain epitaxy | William Hsu, Biswajeet Guha, Chung-Hsun Lin, Anand S. Murthy | 2025-06-10 |
| 12328905 | Cavity spacer for nanowire transistors | William Hsu, Biswajeet Guha, Leonard P. GULER, Souvik Chakrabarty, Jun Sung Kang +1 more | 2025-06-10 |
| 12310060 | Gate-all-around integrated circuit structures having uniform threshold voltages and tight gate endcap tolerances | Dan S. LAVRIC, Dax M. Crum, David J. TOWNER, Orb Acton, Jitendra Kumar Jha +3 more | 2025-05-20 |