Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Tahir Ghani — 504 Patents

Intel: 491 patents #5 of 30,777Top 1%
Sony: 6 patents #6,820 of 25,231Top 30%
TRTahoe Research: 4 patents #1 of 215Top 1%
DPDaedalus Prime: 3 patents #3 of 21Top 15%
Portland, OR: #4 of 9,213 inventorsTop 1%
Oregon: #8 of 28,073 inventorsTop 1%
Overall (All Time): #384 of 4,157,543Top 1%
504 Patents All Time
Tahir Ghani has been granted 504 US patents while listed as an inventor at Intel. The first was granted in 1998 and the most recent in December 2025. Tahir Ghani ranks #384 of 4,157,543 US inventors in our database (top 0.01%). Patent records list Tahir Ghani in Portland, OR, US.

Issued Patents All Time

Showing 1–25 of 504 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12513984 Double-sided integrated circuit transistor structures with depopulated bottom channel regions Varun MISHRA, Peng Zheng, Aaron D. Lilak, Harold W. Kennel, Mauro J. Kobrinsky 2025-12-30
12506127 Package architecture of photonic system with vertically stacked dies having planarized edges Sagar Suthram, Ravindranath V. Mahajan, Debendra Mallik, Omkar G. Karhade, Wilfred Gomes +4 more 2025-12-23
12507449 Gate-all-around integrated circuit structures having necked feature Rishabh Mehandru, Cornelia Weber, Varun MISHRA, Pratik Patel, Woocheol CHUNG +1 more 2025-12-23
12507464 Gate aligned fin cut for advanced integrated circuit structure fabrication Leonard P. GULER, Moh'd A. Hasan, William Hsu, Biswajeet Guha, Charles H. Wallace +2 more 2025-12-23
12506075 Epitaxial source/drain back-side device contact structures with wrap around metallization and protective conformal liner Mohit K. HARAN, Charles H. Wallace, Leonard P. GULER, Sukru YEMENICIOGLU, Mauro J. Kobrinsky 2025-12-23
12501659 Integrated circuit structures having dielectric anchor void Leonard P. GULER, Charles H. Wallace 2025-12-16
12501661 Integrated circuit structures having differentiated channel sizing Rishabh Mehandru, Cornelia Weber, Clifford L. Ong, Sukru YEMENICIOGLU, Brian J. Greene 2025-12-16
12501684 Integrated circuit structures with backside self-aligned penetrating conductive source or drain contact Leonard P. GULER, Mauro J. Kobrinsky, Ehren Mannebach, Makram ABD EL QADER 2025-12-16
12490462 Angled gate or diffusion plugs Leonard P. GULER, Tsai-Shun Chang, Charles H. Wallace, Peter P. Sun, Virupaxi Goornavar 2025-12-02
12484207 SRAM with channel count contrast for greater read stability Clifford L. Ong, Leonard P. GULER, Moh'd A. Hasan 2025-11-25
12484266 Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers Glenn A. Glass, Anand S. Murthy, Biswajeet Guha, Dax M. Crum, Patrick H. Keys +2 more 2025-11-25
12484281 Topside plugs for epitaxial contact formation Leonard P. GULER, Nikhil Mehta, Krishnamurthy Ganesan, Chanaka D. Munasinghe, Charles H. Wallace 2025-11-25
12484272 Source or drain structures with relatively high germanium content Cory Bomberger, Anand S. Murthy, Biswajeet Guha, Anupama Bowonder 2025-11-25
12471349 Contact over active gate structures with uniform and conformal gate insulating cap layers for advanced integrated circuit structure fabrication Leonard P. GULER, Chanaka D. Munasinghe, Charles H. Wallace, Krishnamurthy Ganesan 2025-11-11
12471330 Integrated circuit structures having maximized channel sizing Sukru YEMENICIOGLU, Andy Chi-Hung Wei, Leonard P. GULER, Charles H. Wallace, Mohit K. HARAN 2025-11-11
12471334 Integrated circuit devices with angled transistors formed based on angled wafers Abhishek Sharma, Anand S. Murthy, Wilfred Gomes, Sagar Suthram 2025-11-11
12469780 Integrated circuit structure with recessed self-aligned deep boundary via Mohit K. HARAN, Sukru YEMENICIOGLU, Pratik Patel, Charles H. Wallace, Leonard P. GULER +2 more 2025-11-11
12471362 Integrated circuit structures having ultra-high conductivity global routing Abhishek Sharma, Anand S. Murthy, Sagar Suthram, Pushkar Ranade, Wilfred Gomes +2 more 2025-11-11
12464815 Fin cut in neighboring gate and source or drain regions for advanced integrated circuit structure fabrication Leonard P. GULER, Biswajeet Guha, Tsai-Shun Chang, Sean PURSEL 2025-11-04
12457779 Gate cut structures Leonard P. GULER, Shao Jie Liu, Robert Joachim, Moh'd A. Hasan 2025-10-28
12453160 Deep etch processing for transistors having varying pitch Leonard P. GULER, Moh'd A. Hasan, Charles H. Wallace 2025-10-21
12439669 Co-deposition of titanium and silicon for improved silicon germanium source and drain contacts Debaleena Nandi, Chi Choi, Gilbert Dewey, Harold W. Kennel, Omair Saadat +4 more 2025-10-07
12426360 Wrap-around trench contact structure and methods of fabrication Joseph M. Steigerwald, Oleg Golonzka 2025-09-23
12426316 Method of fabricating integrated circuits with fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric material Leonard P. GULER, Nick Lindert, Biswajeet Guha, Swaminathan Sivakumar 2025-09-23
12426247 Capacitor connections in dielectric layers Travis W. Lajoie, Abhishek A. Sharma, Van H. Le, Chieh-Jen Ku, Pei-Hua Wang +13 more 2025-09-23