Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
SY

Sukru YEMENICIOGLU — 9 Patents

Intel: 9 patents #4,462 of 30,777Top 15%
Portland, OR: #1,884 of 9,213 inventorsTop 25%
Oregon: #4,727 of 28,073 inventorsTop 20%
Overall (All Time): #535,341 of 4,157,543Top 15%
9 Patents All Time
Sukru YEMENICIOGLU has been granted 9 US patents while listed as an inventor at Intel. The first was granted in 2023 and the most recent in December 2025. Sukru YEMENICIOGLU ranks #535,341 of 4,157,543 US inventors in our database (top 12.9%). Patent records list Sukru YEMENICIOGLU in Portland, OR, US.

Patents per Year

Patents granted per year, 2023 to 2025Bar chart with a peak of 6 patents in 2025.peak 62023: 1 patents20232024: 2 patents20242025: 6 patents2025

Issued Patents All Time

Showing 1–9 of 9 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12506059 Vertically spaced intra-level interconnect line metallization for integrated circuit devices Keh-I Lin, Patrick Morrow, Richard E. Schenker, Mauro J. Kobrinsky 2025-12-23
12506075 Epitaxial source/drain back-side device contact structures with wrap around metallization and protective conformal liner Mohit K. HARAN, Charles H. Wallace, Leonard P. GULER, Mauro J. Kobrinsky, Tahir Ghani 2025-12-23
12501661 Integrated circuit structures having differentiated channel sizing Rishabh Mehandru, Cornelia Weber, Clifford L. Ong, Tahir Ghani, Brian J. Greene 2025-12-16
12469780 Integrated circuit structure with recessed self-aligned deep boundary via Mohit K. HARAN, Pratik Patel, Charles H. Wallace, Leonard P. GULER, Conor P. Puls +2 more 2025-11-11
12471330 Integrated circuit structures having maximized channel sizing Tahir Ghani, Andy Chi-Hung Wei, Leonard P. GULER, Charles H. Wallace, Mohit K. HARAN 2025-11-11
12419085 Integrated circuit structures having backside gate tie-down Leonard P. GULER, Mauro J. Kobrinsky, Mohit K. HARAN, Marni Nabors, Tahir Ghani +2 more 2025-09-16
12051692 Integrated circuit structure with front side signal lines and backside power delivery Quan Shi, Marni Nabors, Nikolay RYZHENKO, Xinning Wang, Sivakumar Venkataraman 2024-07-30 $27,313,000
11948874 Vertically spaced intra-level interconnect line metallization for integrated circuit devices Kevin Lin, Patrick Morrow, Richard E. Schenker, Mauro J. Kobrinsky 2024-04-02 $34,819,000
11764219 Metal space centered standard cell architecture to enable higher cell density Harshitha Vishwanath, Renukprasad HIREMATH, Ranjith Kumar, Ruth A. Brain 2023-09-19 $20,015,000