Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Leonard P. GULER — 63 Patents

Intel: 63 patents #448 of 30,777Top 2%
Hillsboro, OR: #42 of 2,365 inventorsTop 2%
Oregon: #486 of 28,073 inventorsTop 2%
Overall (All Time): #35,470 of 4,157,543Top 1%
63 Patents All Time
Leonard P. GULER has been granted 63 US patents while listed as an inventor at Intel. The first was granted in 2018 and the most recent in December 2025. Leonard P. GULER ranks #35,470 of 4,157,543 US inventors in our database (top 0.85%). Patent records list Leonard P. GULER in Hillsboro, OR, US.

Patents per Year

Patents granted per year, 2018 to 2025Bar chart with a peak of 20 patents in 2025.peak 202018: 1 patents20182019: 1 patents20192020: 3 patents20202021: 4 patents20212022: 10 patents20222023: 10 patents20232024: 14 patents20242025: 20 patents2025

Issued Patents All Time

Showing 1–25 of 63 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12506075 Epitaxial source/drain back-side device contact structures with wrap around metallization and protective conformal liner Mohit K. HARAN, Charles H. Wallace, Sukru YEMENICIOGLU, Mauro J. Kobrinsky, Tahir Ghani 2025-12-23
12426316 Method of fabricating integrated circuits with fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric material Nick Lindert, Biswajeet Guha, Swaminathan Sivakumar, Tahir Ghani 2025-09-23
12419085 Integrated circuit structures having backside gate tie-down Mauro J. Kobrinsky, Mohit K. HARAN, Marni Nabors, Tahir Ghani, Charles H. Wallace +2 more 2025-09-16
12408422 Integrated circuit structures with backside gate cut or trench contact cut Charles H. Wallace, Tahir Ghani 2025-09-02
12405526 Extreme ultraviolet lithography patterning with assist features Tahir Ghani, Charles H. Wallace, Hossam A. Abdallah, Dario Farias, Tsuan-Chung CHANG +5 more 2025-09-02
12400913 Contact over active gate structures with conductive trench contact taps for advanced integrated circuit structure fabrication Manish Chandhok, Elijah V. Karpov, Mohit K. HARAN, Reken Patel, Charles H. Wallace +5 more 2025-08-26
12382721 Integrated circuit structures having cut metal gates with dielectric spacer fill Chanaka D. Munasinghe, Makram ABD EL QADER, Marie T. Conte, Saurabh Morarka, Elliot N. Tan +5 more 2025-08-05
12382706 Self-aligned gate endcap (SAGE) architectures with gate-all-around devices Biswajeet Guha, William Hsu, Dax M. Crum, Tahir Ghani 2025-08-05
12369393 Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up approach Dax M. Crum, Biswajeet Guha, Tahir Ghani 2025-07-22
12369392 Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates Michael K. Harper, William Hsu, Biswajeet Guha, Tahir Ghani, Niels Zussblatt +6 more 2025-07-22
12364002 Integrated circuit structures having metal gates with tapered plugs Mohammad HASAN, Biswajeet Guha, Oleg Golonzka, Leah Shoer, Daniel G. Ouellette +2 more 2025-07-15
12364001 Integrated circuit structures with backside gate partial cut or trench contact partial cut Mohammad HASAN, Charles H. Wallace, Tahir Ghani 2025-07-15
12349394 Dielectric isolation layer between a nanowire transistor and a substrate Bruce Beattie, Biswajeet Guha, Jun Sung Kang, William Hsu 2025-07-01
12342612 Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions Biswajeet Guha, Tahir Ghani, Swaminathan Sivakumar 2025-06-24
12328905 Cavity spacer for nanowire transistors William Hsu, Biswajeet Guha, Souvik Chakrabarty, Jun Sung Kang, Bruce Beattie +1 more 2025-06-10
12272688 Selective growth self-aligned gate endcap (SAGE) architectures without fin end gap Zachary Geiger, Glenn A. Glass, Szuya S. Liao 2025-04-08
12266708 Integrated circuit structures having dielectric anchor void Charles H. Wallace, Tahir Ghani 2025-04-01
12249541 Vertical edge blocking (VEB) technique for increasing patterning process margin Chul-Hyun Lim, Paul A. Nyhus, Elliot N. Tan, Charles H. Wallace 2025-03-11
12224350 Self-aligned gate endcap (SAGE) architectures with gate-all-around devices Biswajeet Guha, William Hsu, Dax M. Crum, Tahir Ghani 2025-02-11
12211925 Gate-all-around integrated circuit structures having oxide sub-fins Biswajeet Guha, Tahir Ghani, Swaminathan Sivakumar 2025-01-28
12131989 Vertical metal splitting using helmets and wrap-around dielectric spacers Charles H. Wallace, Paul A. Nyhus 2024-10-29 $18,861,000
12131991 Self aligned gratings for tight pitch interconnects and methods of fabrication Manish Chandhok, Paul A. Nyhus, Gobind Bisht, Jonathan Laib, David Shykind +5 more 2024-10-29 $18,861,000
12080639 Contact over active gate structures with metal oxide layers to inhibit shorting Rami Hourani, Manish Chandhok, Richard E. Schenker, Florian Gstrein, Charles H. Wallace +4 more 2024-09-03 $14,017,000
12068314 Fabrication of gate-all-around integrated circuit structures having adjacent island structures William Hsu, Biswajeet Guha, Martin Weiss, Apratim Dhar, William T. BLANTON +7 more 2024-08-20 $20,163,000
12057491 Self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates Biswajeet Guha, Dax M. Crum, Stephen M. Cea, Tahir Ghani 2024-08-06 $17,070,000