Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Bruce Beattie — 23 Patents

Intel: 21 patents #1,927 of 30,777Top 7%
Portland, OR: #820 of 9,213 inventorsTop 9%
Oregon: #1,851 of 28,073 inventorsTop 7%
Overall (All Time): #178,160 of 4,157,543Top 5%
23 Patents All Time
Bruce Beattie has been granted 23 US patents while listed as an inventor at Intel. The first was granted in 1990 and the most recent in October 2025. Bruce Beattie ranks #178,160 of 4,157,543 US inventors in our database (top 4.3%). Patent records list Bruce Beattie in Portland, OR, US.

Patents per Year

Patents granted per year, 1990 to 2025Bar chart with a peak of 5 patents in 2024.peak 51990: 1 patents19901999: 1 patents2000: 2 patents20002002: 1 patents2003: 1 patents20032015: 1 patents2016: 1 patents20162021: 2 patents2022: 3 patents20222023: 1 patents2024: 5 patents20242025: 4 patents2025

Issued Patents All Time

Showing 1–23 of 23 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12453115 Nanowire transistor structure and method of shaping Erica J. Thompson, Aditya Kasukurti, Ju Hee Kang, Kai Loon Cheong, Biswajeet Guha +1 more 2025-10-21
12349394 Dielectric isolation layer between a nanowire transistor and a substrate Leonard P. GULER, Biswajeet Guha, Jun Sung Kang, William Hsu 2025-07-01
12328905 Cavity spacer for nanowire transistors William Hsu, Biswajeet Guha, Leonard P. GULER, Souvik Chakrabarty, Jun Sung Kang +1 more 2025-06-10
12302632 Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process Jun Sung Kang, Kai Loon Cheong, Erica J. Thompson, Biswajeet Guha, William Hsu +2 more 2025-05-13
11929396 Cavity spacer for nanowire transistors William Hsu, Biswajeet Guha, Leonard P. GULER, Souvik Chakrabarty, Jun Sung Kang +1 more 2024-03-12 $37,196,000
11901458 Dielectric isolation layer between a nanowire transistor and a substrate Leonard P. GULER, Biswajeet Guha, Jun Sung Kang, William Hsu 2024-02-13 $18,546,000
11894368 Gate-all-around integrated circuit structures fabricated using alternate etch selective material Sudipto Naskar, Biswajeet Guha, William Hsu, Tahir Ghani 2024-02-06 $35,892,000
11869973 Nanowire transistor structure and method of shaping Erica J. Thompson, Aditya Kasukurti, Jun Sung Kang, Kai Loon Cheong, Biswajeet Guha +1 more 2024-01-09 $30,329,000
11869891 Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process Jun Sung Kang, Kai Loon Cheong, Erica J. Thompson, Biswajeet Guha, William Hsu +2 more 2024-01-09 $30,329,000
11715787 Self-aligned nanowire Mark Armstrong, Biswajeet Guha, Jun Sung Kang, Tahir Ghani 2023-08-01 $26,467,000
11404578 Dielectric isolation layer between a nanowire transistor and a substrate Leonard P. GULER, Biswajeet Guha, Jun Sung Kang, William Hsu 2022-08-02 $13,520,000
11342411 Cavity spacer for nanowire transistors William Hsu, Biswajeet Guha, Leonard P. GULER, Souvik Chakrabarty, Jun Sung Kang +1 more 2022-05-24 $18,289,000
11276691 Gate-all-around integrated circuit structures having self-aligned source or drain undercut for varied widths Biswajeet Guha, Jun Sung Kang, Stephen M. Cea, Tahir Ghani 2022-03-15 $18,336,000
11205715 Self-aligned nanowire Mark Armstrong, Biswajeet Guha, Jun Sung Kang, Tahir Ghani 2021-12-21 $33,282,000
11069795 Transistors with channel and sub-channel regions with distinct compositions and dimensions Karthik Jambunathan, Glenn A. Glass, Anand S. Murthy, Jun Sung Kang, Anupama Bowonder +3 more 2021-07-20 $44,320,000
9472399 Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates Annalisa Cappellani, Pragyansri Pathi, Abhijit Jayant Pethe 2016-10-18 $9,528,000
9041106 Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates Annalisa Cappellani, Pragyansri Pathi, Abhijit Jayant Pethe 2015-05-26 $20,586,000
6597046 Integrated circuit with multiple gate dielectric structures Robert S. Chau, Reza Arghavani 2003-07-22 $27,595,000
6465358 Post etch clean sequence for making a semiconductor device Michael S. Nashner 2002-10-15 $56,657,000
6124171 Method of forming gate oxide having dual thickness by oxidation process Reza Arghavani, Robert S. Chau, Jack T. Kavalieros, Bob McFadden 2000-09-26 $171,565,000
6087236 Integrated circuit with multiple gate dielectric structures Robert S. Chau, Reza Arghavani 2000-07-11 $279,406,000
5898968 Accessory for cleaning golf club heads and golf balls 1999-05-04
4909185 Cantilever and cold zone assembly for loading and unloading an oven Robert Aldridge 1990-03-20