BB

Bruce Beattie

IN Intel: 20 patents #2,022 of 30,777Top 7%
Overall (All Time): #189,579 of 4,157,543Top 5%
22
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12349394 Dielectric isolation layer between a nanowire transistor and a substrate Leonard P. GULER, Biswajeet Guha, Jun Sung Kang, William Hsu 2025-07-01
12328905 Cavity spacer for nanowire transistors William Hsu, Biswajeet Guha, Leonard P. GULER, Souvik Chakrabarty, Jun Sung Kang +1 more 2025-06-10
12302632 Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process Jun Sung Kang, Kai Loon Cheong, Erica J. Thompson, Biswajeet Guha, William Hsu +2 more 2025-05-13
11929396 Cavity spacer for nanowire transistors William Hsu, Biswajeet Guha, Leonard P. GULER, Souvik Chakrabarty, Jun Sung Kang +1 more 2024-03-12
11901458 Dielectric isolation layer between a nanowire transistor and a substrate Leonard P. GULER, Biswajeet Guha, Jun Sung Kang, William Hsu 2024-02-13
11894368 Gate-all-around integrated circuit structures fabricated using alternate etch selective material Sudipto Naskar, Biswajeet Guha, William Hsu, Tahir Ghani 2024-02-06
11869973 Nanowire transistor structure and method of shaping Erica J. Thompson, Aditya Kasukurti, Jun Sung Kang, Kai Loon Cheong, Biswajeet Guha +1 more 2024-01-09
11869891 Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process Jun Sung Kang, Kai Loon Cheong, Erica J. Thompson, Biswajeet Guha, William Hsu +2 more 2024-01-09
11715787 Self-aligned nanowire Mark Armstrong, Biswajeet Guha, Jun Sung Kang, Tahir Ghani 2023-08-01
11404578 Dielectric isolation layer between a nanowire transistor and a substrate Leonard P. GULER, Biswajeet Guha, Jun Sung Kang, William Hsu 2022-08-02
11342411 Cavity spacer for nanowire transistors William Hsu, Biswajeet Guha, Leonard P. GULER, Souvik Chakrabarty, Jun Sung Kang +1 more 2022-05-24
11276691 Gate-all-around integrated circuit structures having self-aligned source or drain undercut for varied widths Biswajeet Guha, Jun Sung Kang, Stephen M. Cea, Tahir Ghani 2022-03-15
11205715 Self-aligned nanowire Mark Armstrong, Biswajeet Guha, Jun Sung Kang, Tahir Ghani 2021-12-21
11069795 Transistors with channel and sub-channel regions with distinct compositions and dimensions Karthik Jambunathan, Glenn A. Glass, Anand S. Murthy, Jun Sung Kang, Anupama Bowonder +3 more 2021-07-20
9472399 Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates Annalisa Cappellani, Pragyansri Pathi, Abhijit Jayant Pethe 2016-10-18
9041106 Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates Annalisa Cappellani, Pragyansri Pathi, Abhijit Jayant Pethe 2015-05-26
6597046 Integrated circuit with multiple gate dielectric structures Robert S. Chau, Reza Arghavani 2003-07-22
6465358 Post etch clean sequence for making a semiconductor device Michael S. Nashner 2002-10-15
6124171 Method of forming gate oxide having dual thickness by oxidation process Reza Arghavani, Robert S. Chau, Jack T. Kavalieros, Bob McFadden 2000-09-26
6087236 Integrated circuit with multiple gate dielectric structures Robert S. Chau, Reza Arghavani 2000-07-11
5898968 Accessory for cleaning golf club heads and golf balls — 1999-05-04
4909185 Cantilever and cold zone assembly for loading and unloading an oven Robert Aldridge 1990-03-20