Issued Patents All Time
Showing 25 most recent of 56 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11380619 | Semiconductor devices including cobalt alloys and fabrication methods thereof | Junichi Koike | 2022-07-05 |
| 11011379 | Capped ALD films for doping fin-shaped channel regions of 3-D IC transistors | Samantha Tan, Bhadri N. Varadarajan, Adrien LaVoie, Ananda Banerji, Jun Qian +1 more | 2021-05-18 |
| 10796995 | Semiconductor devices including a first cobalt alloy in a first barrier layer and a second cobalt alloy in a second barrier layer | Junichi Koike | 2020-10-06 |
| 10741405 | Selective self-aligned patterning of silicon germanium, germanium and type III/V materials using a sulfur-containing mask | Daniel Peter, Samantha Tan, Yang Pan | 2020-08-11 |
| 10559468 | Capped ALD films for doping fin-shaped channel regions of 3-D IC transistors | Samantha Tan, Bhadri N. Varadarajan, Adrien LaVoie, Ananda Banerji, Jun Qian +1 more | 2020-02-11 |
| 10068981 | Rare earth metal surface-activated plasma doping on semiconductor substrates | Yunsang Kim | 2018-09-04 |
| 10043672 | Selective self-aligned patterning of silicon germanium, germanium and type III/V materials using a sulfur-containing mask | Daniel Peter, Samantha Tan, Yang Pan | 2018-08-07 |
| 9997357 | Capped ALD films for doping fin-shaped channel regions of 3-D IC transistors | Samantha Tan, Bhadri N. Varadarajan, Adrien LaVoie, Ananda Banerji, Jun Qian +1 more | 2018-06-12 |
| 9922977 | Transistor with threshold voltage set notch and method of fabrication thereof | Pushkar Ranade, Lucian Shifren, Scott E. Thompson, Catherine de Villeneuve | 2018-03-20 |
| 9478411 | Method to tune TiOx stoichiometry using atomic layer deposited Ti film to minimize contact resistance for TiOx/Ti based MIS contact scheme for CMOS | Shruti Vivek Thombare, Ishtak Karim, Sanjay Gopinath, Michal Danek | 2016-10-25 |
| 9418987 | Transistor with threshold voltage set notch and method of fabrication thereof | Pushkar Ranade, Lucian Shifren, Scott E. Thompson, Catherine de Villeneuve | 2016-08-16 |
| 9396961 | Integrated etch/clean for dielectric etch applications | Shashank Deshmukh, Eric A. Hudson, Tom A. Kamp, Samantha Tan, Gerardo Delgadino | 2016-07-19 |
| 9153486 | CVD based metal/semiconductor OHMIC contact for high volume manufacturing applications | Jeffrey Marks, Benjamin A. Bonner | 2015-10-06 |
| 8759872 | Transistor with threshold voltage set notch and method of fabrication thereof | Pushkar Ranade, Lucian Shifren, Scott E. Thompson, Catherine de Villeneuve | 2014-06-24 |
| 8501568 | Method of forming flash memory with ultraviolet treatment | Mihaela Balseanu, Vladimir Zubkov, Li-Qun Xia, Atif Noori, Derek R. Witty +1 more | 2013-08-06 |
| 8252653 | Method of forming a non-volatile memory having a silicon nitride charge trap layer | Mihaela Balseanu, Vladimir Zubkov, Li-Qun Xia, Atif Noori, Derek R. Witty +1 more | 2012-08-28 |
| 8173495 | Semiconductor on insulator | Been-Yih Jin, Robert S. Chau | 2012-05-08 |
| 7955510 | Oxide etch with NH4-NF3 chemistry | Chien-Teh Kao, Xinliang Lu | 2011-06-07 |
| 7875932 | Semiconductor on insulator apparatus | Been-Yih Jin, Robert S. Chau | 2011-01-25 |
| 7851385 | Low temperature conformal oxide formation and applications | Matthew Spuller, Melody Agustin, Meiyee Shek, Li-Qun Xia | 2010-12-14 |
| 7816205 | Method of forming non-volatile memory having charge trap layer with compositional gradient | Mihaela Balseanu, Vladimir Zubkov, Li-Qun Xia, Atif Noori, Derek R. Witty +1 more | 2010-10-19 |
| 7678662 | Memory cell having stressed layers | Ellie Yieh, Hichem M'Saad | 2010-03-16 |
| 7674727 | Nitrous oxide anneal of TEOS/ozone CVD for improved gapfill | Zheng Yuan, Shankar Venkataraman | 2010-03-09 |
| 7671414 | Semiconductor on insulator apparatus | Been-Yih Jin, Robert S. Chau | 2010-03-02 |
| 7563680 | Substrate having silicon germanium material and stressed silicon nitride layer | — | 2009-07-21 |