AB

Anupama Bowonder

IN Intel: 20 patents #2,022 of 30,777Top 7%
University of California: 2 patents #4,561 of 18,278Top 25%
Overall (All Time): #188,515 of 4,157,543Top 5%
22
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12426299 Fin shaping and integrated circuit structures resulting therefrom Szuya S. Liao, Rahul Pandey, Rishabh Mehandru, Pratik A. Patel 2025-09-23
12237420 Fin smoothing and integrated circuit structures resulting therefrom Cory Bomberger, Anand S. Murthy, Tahir Ghani 2025-02-25
12021149 Fin smoothing and integrated circuit structures resulting therefrom Cory Bomberger, Anand S. Murthy, Tahir Ghani 2024-06-25
11984449 Channel structures with sub-fin dopant diffusion blocking layers Cory Bomberger, Anand S. Murthy, Stephen M. Cea, Biswajeet Guha, Tahir Ghani 2024-05-14
11923412 Sub-fin leakage reduction for template strained materials Rishabh Mehandru, Stephen M. Cea, Juhyung Nam, Willy Rachmady 2024-03-05
11901457 Fin shaping and integrated circuit structures resulting therefrom Szuya S. Liao, Rahul Pandey, Rishabh Mehandru, Pratik A. Patel 2024-02-13
11757037 Epitaxial oxide plug for strained transistors Karthik Jambunathan, Biswajeet Guha, Anand S. Murthy, Tahir Ghani 2023-09-12
11735630 Integrated circuit structures with source or drain dopant diffusion blocking layers Cory Bomberger, Anand S. Murthy, Aaron A. Budrevich, Tahir Ghani 2023-08-22
11682731 Fin smoothing and integrated circuit structures resulting therefrom Cory Bomberger, Anand S. Murthy, Tahir Ghani 2023-06-20
11600696 Sub-fin leakage reduction for template strained materials Rishabh Mehandru, Stephen M. Cea, Juhyung Nam, Willy Rachmady 2023-03-07
11521968 Channel structures with sub-fin dopant diffusion blocking layers Cory Bomberger, Anand S. Murthy, Stephen M. Cea, Biswajeet Guha, Tahir Ghani 2022-12-06
11495683 Multiple strain states in epitaxial transistor channel through the incorporation of stress-relief defects within an underlying seed material Aaron D. Lilak, Patrick H. Keys, Sayed Hasan, Stephen M. Cea 2022-11-08
11462536 Integrated circuit structures having asymmetric source and drain structures Rishabh Mehandru, Mark Bohr, Tahir Ghani 2022-10-04
11456357 Self-aligned gate edge architecture with alternate channel material Biswajeet Guha, William Hsu, Szuya S. Liao, Mehmet O. Baykan, Tahir Ghani 2022-09-27
11430868 Buried etch-stop layer to help control transistor source/drain depth Rishabh Mehandru, Biswajeet Guha, Anand S. Murthy, Tahir Ghani, Stephen M. Cea 2022-08-30
11374100 Source or drain structures with contact etch stop layer Cory Bomberger, Rishabh Mehandru, Biswajeet Guha, Anand S. Murthy, Tahir Ghani 2022-06-28
11251302 Epitaxial oxide plug for strained transistors Karthik Jambunathan, Biswajeet Guha, Anand S. Murthy, Tahir Ghani 2022-02-15
11152461 Semiconductor layer between source/drain regions and gate spacers Rishabh Mehandru, Biswajeet Guha, Tahir Ghani, Stephen M. Cea, William Hsu +2 more 2021-10-19
11069795 Transistors with channel and sub-channel regions with distinct compositions and dimensions Karthik Jambunathan, Glenn A. Glass, Anand S. Murthy, Jun Sung Kang, Bruce Beattie +3 more 2021-07-20
10886272 Techniques for forming dual-strain fins for co-integrated n-MOS and p-MOS devices Stephen M. Cea, Rishabh Mehandru, Anand S. Murthy, Tahir Ghani 2021-01-05
9117893 Tunneling transistor suitable for low voltage operation Chenming Hu, Pratik A. Patel, Daniel Chou, Prashant Majhi 2015-08-25
8384122 Tunneling transistor suitable for low voltage operation Chenming Hu, Pratik A. Patel, Daniel Chou, Prashant Majhi 2013-02-26