Issued Patents All Time
Showing 25 most recent of 117 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12328864 | 3D 1T1C stacked dram structure and method to fabricate | Sean T. Ma, Abhishek A. Sharma | 2025-06-10 |
| 12288807 | Amorphization and regrowth of source-drain regions from the bottom-side of a semiconductor assembly | Rishabh Mehandru, Willy Rachmady, Harold W. Kennel, Tahir Ghani | 2025-04-29 |
| 12288810 | Backside contact structures and fabrication for metal on both sides of devices | Patrick Morrow, Rishabh Mehandru, Kimin Jun | 2025-04-29 |
| 12288813 | Gate-all-around integrated circuit structures having insulator fin on insulator substrate | Rishabh Mehandru, Cory E. Weber, Willy Rachmady, Varun MISHRA | 2025-04-29 |
| 12255137 | Sideways vias in isolation areas to contact interior layers in stacked devices | Ehren Mannebach, Hui Jae Yoo, Patrick Morrow, Anh Phan, Willy Rachmady +3 more | 2025-03-18 |
| 12224202 | Forming an oxide volume within a fin | Cheng-Ying Huang, Gilbert Dewey, Jack T. Kavalieros, Ehren Mannebach, Patrick Morrow +3 more | 2025-02-11 |
| 12199098 | Fin doping and integrated circuit structures resulting therefrom | Cory E. Weber, Stephen M. Cea, Leonard C. Pipes, Seahee Hwangbo, Rishabh Mehandru +3 more | 2025-01-14 |
| 12148806 | Stacked source-drain-gate connection and process for forming such | Ehren Mannebach, Hui Jae Yoo, Patrick Morrow, Anh Phan, Willy Rachmady +2 more | 2024-11-19 |
| 12107085 | Interconnect techniques for electrically connecting source/drain regions of stacked transistors | Gilbert Dewey, Cheng-Ying Huang, Christopher J. Jezewski, Ehren Mannebach, Rishabh Mehandru +4 more | 2024-10-01 |
| 12100623 | Vertically stacked finFETs and shared gate patterning | Sean T. Ma, Justin R. Weber, Rishabh Mehandru, Stephen M. Cea, Patrick Morrow +1 more | 2024-09-24 |
| 12080605 | Backside contacts for semiconductor devices | Ehren Mannebach, Anh Phan, Richard E. Schenker, Stephanie A. Bojarski, Willy Rachmady +4 more | 2024-09-03 |
| 12057494 | Stacked transistors | Patrick Morrow, Rishabh Mehandru | 2024-08-06 |
| 12051723 | PN-body-tied field effect transistors | Kerryann Marrietta Foley, Sayed Hasan, Patrick Morrow, Willy Rachmady | 2024-07-30 |
| 12033896 | Isolation wall stressor structures to improve channel stress and their methods of fabrication | Christopher J. Jezewski, Willy Rachmady, Rishabh Mehandru, Gilbert Dewey, Anh Phan | 2024-07-09 |
| 12020929 | Epitaxial layer with substantially parallel sides | Cheng-Ying Huang, Gilbert Dewey, Jack T. Kavalieros, Ehren Mannebach, Patrick Morrow +3 more | 2024-06-25 |
| 11996408 | Leave-behind protective layer having secondary purpose | Anh Phan, Ehren Mannebach, Cheng-Ying Huang, Stephanie A. Bojarski, Gilbert Dewey +2 more | 2024-05-28 |
| 11942416 | Sideways vias in isolation areas to contact interior layers in stacked devices | Ehren Mannebach, Hui Jae Yoo, Patrick Morrow, Anh Phan, Willy Rachmady +3 more | 2024-03-26 |
| 11935891 | Non-silicon N-type and P-type stacked transistors for integrated circuit devices | Gilbert Dewey, Patrick Morrow, Ravi Pillarisetty, Rishabh Mehandru, Cheng-Ying Huang +1 more | 2024-03-19 |
| 11935933 | Backside contact structures and fabrication for metal on both sides of devices | Patrick Morrow, Rishabh Mehandru, Kimin Jun | 2024-03-19 |
| 11916118 | Stacked source-drain-gate connection and process for forming such | Ehren Mannebach, Hui Jae Yoo, Patrick Morrow, Anh Phan, Willy Rachmady +2 more | 2024-02-27 |
| 11894372 | Stacked trigate transistors with dielectric isolation and process for forming such | Willy Rachmady, Cheng-Ying Huang, Gilbert Dewey, Patrick Morrow, Anh Phan +2 more | 2024-02-06 |
| 11894262 | Back side processing of integrated circuit structures to form insulation structure between adjacent transistor structures | Rishabh Mehandru, Patrick Morrow | 2024-02-06 |
| 11869894 | Metallization structures for stacked device connectivity and their methods of fabrication | Anh Phan, Patrick Morrow, Willy Rachmady, Gilbert Dewey, Jessica M. Torres +6 more | 2024-01-09 |
| 11862702 | Gate-all-around integrated circuit structures having insulator FIN on insulator substrate | Rishabh Mehandru, Cory E. Weber, Willy Rachmady, Varun MISHRA | 2024-01-02 |
| 11849572 | 3D 1T1C stacked DRAM structure and method to fabricate | Sean T. Ma, Abhishek A. Sharma | 2023-12-19 |