| 12457778 |
Conductive contacts wrapped around epitaxial source or drain regions |
Leonard P. GULER, Saurabh Morarka, Sikandar Abbas, Moh'd A. Hasan |
2025-10-28 |
|
| 12439669 |
Co-deposition of titanium and silicon for improved silicon germanium source and drain contacts |
Debaleena Nandi, Chi Choi, Harold W. Kennel, Omair Saadat, Jitendra Kumar Jha +4 more |
2025-10-07 |
|
| 12426342 |
Low germanium, high boron silicon rich capping layer for PMOS contact resistance thermal stability |
Debaleena Nandi, Cory Bomberger, Anand S. Murthy, Mauro J. Kobrinsky, Rushabh SHAH +6 more |
2025-09-23 |
|
| 12414339 |
Formation of gate spacers for strained PMOS gate-all-around transistor structures |
Ashish Agrawal, Siddharth Chouksey, Jack T. Kavalieros, Cheng-Ying Huang |
2025-09-09 |
|
| 12388011 |
Top gate recessed channel CMOS thin film transistor and methods of fabrication |
Ryan Keech, Cory Bomberger, Cheng-Ying Huang, Ashish Agrawal, Willy Rachmady +1 more |
2025-08-12 |
|
| 12376362 |
Field effect transistors with a gated oxide semiconductor source/drain spacer |
Rafael Rios, Van H. Le, Jack T. Kavalieros |
2025-07-29 |
|
| 12369399 |
Gate-to-gate isolation for stacked transistor architecture via selective dielectric deposition structure |
Willy Rachmady, Sudipto Naskar, Cheng-Ying Huang, Marko Radosavljevic, Nicole K. Thomas +2 more |
2025-07-22 |
|
| 12349416 |
Transistor structures with a metal oxide contact buffer and a method of fabricating the transistor structures |
Abhishek A. Sharma, Van H. Le, Jack T. Kavalieros, Shriram Shivaraman, Seung Hoon Sung +4 more |
2025-07-01 |
|
| 12342574 |
Contact resistance reduction in transistor devices with metallization on both sides |
Koustav Ganguly, Ryan Keech, Subrina RAFIQUE, Glenn A. Glass, Anand S. Murthy +2 more |
2025-06-24 |
|
| 12328927 |
Low resistance and reduced reactivity approaches for fabricating contacts and the resulting structures |
Nazila Haratipour, Siddharth Chouksey, Arnab Sen Gupta, Christopher J. Jezewski, I-Cheng Tung +2 more |
2025-06-10 |
|
| 12288803 |
Transistor with isolation below source and drain |
Willy Rachmady, Cheng-Ying Huang, Matthew V. Metz, Nicholas G. Minutillo, Sean T. Ma +3 more |
2025-04-29 |
|
| 12255137 |
Sideways vias in isolation areas to contact interior layers in stacked devices |
Ehren Mannebach, Aaron D. Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan +3 more |
2025-03-18 |
|
| 12224202 |
Forming an oxide volume within a fin |
Cheng-Ying Huang, Jack T. Kavalieros, Aaron D. Lilak, Ehren Mannebach, Patrick Morrow +3 more |
2025-02-11 |
|
| 12191395 |
Dual gate control for trench shaped thin film transistors |
Abhishek A. Sharma, Van H. Le, Jack T. Kavalieros, Shriram Shivaraman, Benjamin Chu-Kung +2 more |
2025-01-07 |
|
| 12183668 |
Thin-film transistors and MIM capacitors in exclusion zones |
Abhishek A. Sharma, Willy Rachmady, Cheng-Ying Huang, Rajat K. Paul |
2024-12-31 |
$16,542,000 |
| 12183739 |
Ribbon or wire transistor stack with selective dipole threshold voltage shifter |
Nicole K. Thomas, Eric Mattson, Sudarat Lee, Scott B. Clendenning, Tobias Brown-Heft +6 more |
2024-12-31 |
$16,542,000 |
| 12183831 |
Self-aligned contacts for thin film transistors |
Van H. Le, Abhishek A. Sharma, Benjamin Chu-Kung, Ravi Pillarisetty, Miriam Reshotko +4 more |
2024-12-31 |
$16,542,000 |
| 12170319 |
Dual contact process with stacked metal layers |
Kevin T. Cook, Anand S. Murthy, Nazila Haratipour, Ralph T. Troeger, Christopher J. Jezewski +1 more |
2024-12-17 |
$33,648,000 |
| 12148806 |
Stacked source-drain-gate connection and process for forming such |
Ehren Mannebach, Aaron D. Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan +2 more |
2024-11-19 |
$25,575,000 |
| 12142689 |
Transistor including wrap around source and drain contacts |
Sean T. Ma, Abhishek A. Sharma, Jack T. Kavalieros, Van H. Le |
2024-11-12 |
$28,491,000 |
| 12125917 |
Thin film transistors having double gates |
Abhishek A. Sharma, Van H. Le, Jack T. Kavalieros, Tahir Ghani |
2024-10-22 |
$18,859,000 |
| 12119409 |
Multi-layer crystalline back gated thin film transistor |
Van H. Le, Abhishek A. Sharma, Kent Millard, Jack T. Kavalieros, Shriram Shivaraman +6 more |
2024-10-15 |
$19,078,000 |
| 12120865 |
Arrays of double-sided dram cells including capacitors on the frontside and backside of a stacked transistor structure |
Cheng-Ying Huang, Ashish Agrawal, Abhishek A. Sharma, Wilfred Gomes, Jack T. Kavalieros |
2024-10-15 |
$19,078,000 |
| 12119387 |
Low resistance approaches for fabricating contacts and the resulting structures |
Nazila Haratipour, Siddharth Chouksey, Jack T. Kavalieros, Jitendra Kumar Jha, Matthew V. Metz +6 more |
2024-10-15 |
$19,078,000 |
| 12107085 |
Interconnect techniques for electrically connecting source/drain regions of stacked transistors |
Aaron D. Lilak, Cheng-Ying Huang, Christopher J. Jezewski, Ehren Mannebach, Rishabh Mehandru +4 more |
2024-10-01 |
$20,560,000 |
