Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
RK

Ryan Keech — 18 Patents

Intel: 18 patents #2,313 of 30,777Top 8%
Portland, OR: #1,043 of 9,213 inventorsTop 15%
Oregon: #2,430 of 28,073 inventorsTop 9%
Overall (All Time): #245,716 of 4,157,543Top 6%
18 Patents All Time
Ryan Keech has been granted 18 US patents while listed as an inventor at Intel. The first was granted in 2021 and the most recent in August 2025. Ryan Keech ranks #245,716 of 4,157,543 US inventors in our database (top 5.9%). Patent records list Ryan Keech in Portland, OR, US.

Issued Patents All Time

Showing 1–18 of 18 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12388011 Top gate recessed channel CMOS thin film transistor and methods of fabrication Gilbert Dewey, Cory Bomberger, Cheng-Ying Huang, Ashish Agrawal, Willy Rachmady +1 more 2025-08-12
12342574 Contact resistance reduction in transistor devices with metallization on both sides Koustav Ganguly, Subrina RAFIQUE, Glenn A. Glass, Anand S. Murthy, Ehren Mannebach +2 more 2025-06-24
12342611 Source or drain structures with vertical trenches Nicholas G. Minutillo, Anand S. Murthy, Aaron A. Budrevich, Peter Wells 2025-06-24
12288808 High aspect ratio source or drain structures with abrupt dopant profile Anand S. Murthy, Nicholas G. Minutillo, Suresh Vishwanath, Mohammad HASAN, Biswajeet Guha +1 more 2025-04-29
12266570 Self-aligned interconnect structures and methods of fabrication Kimin Jun, Souvik Ghosh, Willy Rachmady, Ashish Agrawal, Siddharth Chouksey +5 more 2025-04-01
12119387 Low resistance approaches for fabricating contacts and the resulting structures Gilbert Dewey, Nazila Haratipour, Siddharth Chouksey, Jack T. Kavalieros, Jitendra Kumar Jha +6 more 2024-10-15 $19,078,000
12094881 Arsenic-doped epitaxial source/drain regions for NMOS Anand S. Murthy, Nicholas G. Minutillo, Ritesh Jhaveri 2024-09-17 $19,251,000
11996404 Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material Cheng-Ying Huang, Gilbert Dewey, Ashish Agrawal, Kimin Jun, Willy Rachmady +5 more 2024-05-28 $30,739,000
11973143 Source or drain structures for germanium N-channel devices Benjamin Chu-Kung, Subrina RAFIQUE, Devin Merrill, Ashish Agrawal, Harold W. Kennel +4 more 2024-04-30 $26,151,000
11935887 Source or drain structures with vertical trenches Nicholas G. Minutillo, Anand S. Murthy, Aaron A. Budrevich, Peter Wells 2024-03-19 $28,784,000
11929320 Top gate recessed channel CMOS thin film transistor in the back end of line and methods of fabrication Gilbert Dewey, Cory Bomberger, Cheng-Ying Huang, Ashish Agrawal, Willy Rachmady +1 more 2024-03-12 $37,196,000
11804523 High aspect ratio source or drain structures with abrupt dopant profile Anand S. Murthy, Nicholas G. Minutillo, Suresh Vishwanath, Mohammad HASAN, Biswajeet Guha +1 more 2023-10-31 $30,374,000
11610889 Arsenic-doped epitaxial, source/drain regions for NMOS Anand S. Murthy, Nicholas G. Minutillo, Ritesh Jhaveri 2023-03-21 $20,076,000
11552169 Source or drain structures with phosphorous and arsenic co-dopants Anand S. Murthy, Nicholas G. Minutillo, Suresh Vishwanath 2023-01-10 $14,061,000
11482621 Vertically stacked CMOS with upfront M0 interconnect Willy Rachmady, Patrick Morrow, Aaron D. Lilak, Rishabh Mehandru, Cheng-Ying Huang +4 more 2022-10-25 $11,792,000
11328988 Top gate recessed channel CMOS thin film transistor in the back end of line and methods of fabrication Gilbert Dewey, Cory Bomberger, Cheng-Ying Huang, Ashish Agrawal, Willy Rachmady +1 more 2022-05-10 $19,182,000
11244943 Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material Cheng-Ying Huang, Gilbert Dewey, Ashish Agrawal, Kimin Jun, Willy Rachmady +5 more 2022-02-08 $27,206,000
11164785 Three-dimensional integrated circuits (3DICs) including upper-level transistors with epitaxial source and drain material Ashish Agrawal, Gilbert Dewey, Cheng-Ying Huang, Willy Rachmady, Anand S. Murthy +1 more 2021-11-02 $26,002,000