Issued Patents All Time
Showing 25 most recent of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12342574 | Contact resistance reduction in transistor devices with metallization on both sides | Koustav Ganguly, Ryan Keech, Subrina RAFIQUE, Glenn A. Glass, Anand S. Murthy +2 more | 2025-06-24 |
| 12255137 | Sideways vias in isolation areas to contact interior layers in stacked devices | Aaron D. Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan, Willy Rachmady +3 more | 2025-03-18 |
| 12230635 | Gate-all-around integrated circuit structures having depopulated channel structures using selective bottom-up approach | Nicole K. Thomas, Cheng-Ying Huang, Marko Radosavljevic | 2025-02-18 |
| 12224202 | Forming an oxide volume within a fin | Cheng-Ying Huang, Gilbert Dewey, Jack T. Kavalieros, Aaron D. Lilak, Patrick Morrow +3 more | 2025-02-11 |
| 12148806 | Stacked source-drain-gate connection and process for forming such | Aaron D. Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan, Willy Rachmady +2 more | 2024-11-19 |
| 12107085 | Interconnect techniques for electrically connecting source/drain regions of stacked transistors | Aaron D. Lilak, Gilbert Dewey, Cheng-Ying Huang, Christopher J. Jezewski, Rishabh Mehandru +4 more | 2024-10-01 |
| 12080605 | Backside contacts for semiconductor devices | Aaron D. Lilak, Anh Phan, Richard E. Schenker, Stephanie A. Bojarski, Willy Rachmady +4 more | 2024-09-03 |
| 12020929 | Epitaxial layer with substantially parallel sides | Cheng-Ying Huang, Gilbert Dewey, Jack T. Kavalieros, Aaron D. Lilak, Patrick Morrow +3 more | 2024-06-25 |
| 11996408 | Leave-behind protective layer having secondary purpose | Aaron D. Lilak, Anh Phan, Cheng-Ying Huang, Stephanie A. Bojarski, Gilbert Dewey +2 more | 2024-05-28 |
| 11996411 | Stacked forksheet transistors | Cheng-Ying Huang, Gilbert Dewey, Anh Phan, Nicole K. Thomas, Urusa Alaan +8 more | 2024-05-28 |
| 11942416 | Sideways vias in isolation areas to contact interior layers in stacked devices | Aaron D. Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan, Willy Rachmady +3 more | 2024-03-26 |
| 11916118 | Stacked source-drain-gate connection and process for forming such | Aaron D. Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan, Willy Rachmady +2 more | 2024-02-27 |
| 11894372 | Stacked trigate transistors with dielectric isolation and process for forming such | Willy Rachmady, Cheng-Ying Huang, Gilbert Dewey, Aaron D. Lilak, Patrick Morrow +2 more | 2024-02-06 |
| 11862636 | Gate-all-around integrated circuit structures having depopulated channel structures using selective bottom-up approach | Nicole K. Thomas, Cheng-Ying Huang, Marko Radosavljevic | 2024-01-02 |
| 11830933 | Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up oxidation approach | Willy Rachmady, Gilbert Dewey, Jack T. Kavalieros, Aaron D. Lilak, Patrick Morrow +2 more | 2023-11-28 |
| 11798838 | Capacitance reduction for semiconductor devices based on wafer bonding | Aaron D. Lilak, Rishabh Mehandru, Hui Jae Yoo, Patrick Morrow, Kevin Lin | 2023-10-24 |
| 11769814 | Device including air gapping of gate spacers and other dielectrics and process for providing such | Aaron D. Lilak, Hui Jae Yoo, Patrick Morrow, Kevin Lin, Tristan A. Tronic | 2023-09-26 |
| 11764104 | Forming an oxide volume within a fin | Cheng-Ying Huang, Gilbert Dewey, Jack T. Kavalieros, Aaron D. Lilak, Patrick Morrow +3 more | 2023-09-19 |
| 11764263 | Gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches | Anh Phan, Aaron D. Lilak, Willy Rachmady, Gilbert Dewey, Cheng-Ying Huang +3 more | 2023-09-19 |
| 11742346 | Interconnect techniques for electrically connecting source/drain regions of stacked transistors | Aaron D. Lilak, Gilbert Dewey, Cheng-Ying Huang, Christopher J. Jezewski, Rishabh Mehandru +4 more | 2023-08-29 |
| 11676966 | Stacked transistors having device strata with different channel widths | Gilbert Dewey, Jack T. Kavalieros, Willy Rachmady, Cheng-Ying Huang, Matthew V. Metz +4 more | 2023-06-13 |
| 11672133 | Vertically stacked memory elements with air gap | Aaron D. Lilak, Patrick Morrow, Hui Jae Yoo, Sean T. Ma, Scott B. Clendenning +2 more | 2023-06-06 |
| 11664377 | Forksheet transistor architectures | Aaron D. Lilak, Rishabh Mehandru, Patrick Morrow, Willy Rachmady | 2023-05-30 |
| 11646352 | Stacked source-drain-gate connection and process for forming such | Aaron D. Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan, Willy Rachmady +2 more | 2023-05-09 |
| 11616060 | Techniques for forming gate structures for transistors arranged in a stacked configuration on a single fin structure | Aaron D. Lilak, Gilbert Dewey, Willy Rachmady, Rami Hourani, Stephanie A. Bojarski +2 more | 2023-03-28 |