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USPTO Patent Rankings Data through Dec 31, 2025
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Leonard P. GULER — 16 Patents

Overall (All Time): N/A of 4,157,543
16 Patents All Time
Leonard P. GULER has been granted 16 US patents. All of these patents were granted in 2025.

Issued Patents All Time

Showing 1–16 of 16 patents

Patent #TitleCo-InventorsDate
12507464 Gate aligned fin cut for advanced integrated circuit structure fabrication Moh'd A. Hasan, William Hsu, Biswajeet Guha, Charles H. Wallace, Tahir Ghani +2 more 2025-12-23
12501684 Integrated circuit structures with backside self-aligned penetrating conductive source or drain contact Mauro J. Kobrinsky, Ehren Mannebach, Makram ABD EL QADER, Tahir Ghani 2025-12-16
12501659 Integrated circuit structures having dielectric anchor void Charles H. Wallace, Tahir Ghani 2025-12-16
12490462 Angled gate or diffusion plugs Tsai-Shun Chang, Charles H. Wallace, Peter P. Sun, Tahir Ghani, Virupaxi Goornavar 2025-12-02
12484247 Gate-all-around integrated circuit structures having backside contact with enhanced area relative to epitaxial source Joseph D'SILVA, Mauro J. Kobrinsky, Shaun MILLS, Nafees Kabir, Makram ABD EL QADER 2025-11-25
12484281 Topside plugs for epitaxial contact formation Nikhil Mehta, Krishnamurthy Ganesan, Chanaka D. Munasinghe, Tahir Ghani, Charles H. Wallace 2025-11-25
12484207 SRAM with channel count contrast for greater read stability Clifford L. Ong, Moh'd A. Hasan, Tahir Ghani 2025-11-25
12471330 Integrated circuit structures having maximized channel sizing Sukru YEMENICIOGLU, Tahir Ghani, Andy Chi-Hung Wei, Charles H. Wallace, Mohit K. HARAN 2025-11-11
12469780 Integrated circuit structure with recessed self-aligned deep boundary via Mohit K. HARAN, Sukru YEMENICIOGLU, Pratik Patel, Charles H. Wallace, Conor P. Puls +2 more 2025-11-11
12471349 Contact over active gate structures with uniform and conformal gate insulating cap layers for advanced integrated circuit structure fabrication Chanaka D. Munasinghe, Charles H. Wallace, Tahir Ghani, Krishnamurthy Ganesan 2025-11-11
12464815 Fin cut in neighboring gate and source or drain regions for advanced integrated circuit structure fabrication Biswajeet Guha, Tahir Ghani, Tsai-Shun Chang, Sean PURSEL 2025-11-04
12457771 Plug and recess process for dual metal gate on stacked nanoribbon devices Nicole K. Thomas, Michael K. Harper, Marko Radosavljevic, Thoe Michaelos 2025-10-28
12457778 Conductive contacts wrapped around epitaxial source or drain regions Gilbert Dewey, Saurabh Morarka, Sikandar Abbas, Moh'd A. Hasan 2025-10-28
12457779 Gate cut structures Shao Jie Liu, Robert Joachim, Moh'd A. Hasan, Tahir Ghani 2025-10-28
12453160 Deep etch processing for transistors having varying pitch Moh'd A. Hasan, Tahir Ghani, Charles H. Wallace 2025-10-21
12444685 Backside electrical contact for PMOS epitaxial voltage supply Clifford L. Ong, Zheng Guo, Eirc A. Karl, Smita Shridharan, Mauro J. Kobrinsky +3 more 2025-10-14