Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
WH

William Hsu — 47 Patents

Intel: 41 patents #856 of 30,777Top 3%
HTHr Textron: 5 patents #4 of 83Top 5%
TETextron: 1 patents #316 of 575Top 55%
Hillsboro, OR: #71 of 2,365 inventorsTop 4%
Oregon: #756 of 28,073 inventorsTop 3%
Overall (All Time): #59,703 of 4,157,543Top 2%
47 Patents All Time
William Hsu has been granted 47 US patents while listed as an inventor at Intel. The first was granted in 1980 and the most recent in December 2025. William Hsu ranks #59,703 of 4,157,543 US inventors in our database (top 1.4%). Patent records list William Hsu in Hillsboro, OR, US.

Issued Patents All Time

Showing 1–25 of 47 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12507464 Gate aligned fin cut for advanced integrated circuit structure fabrication Leonard P. GULER, Moh'd A. Hasan, Biswajeet Guha, Charles H. Wallace, Tahir Ghani +2 more 2025-12-23
12453115 Nanowire transistor structure and method of shaping Erica J. Thompson, Aditya Kasukurti, Ju Hee Kang, Kai Loon Cheong, Biswajeet Guha +1 more 2025-10-21
12402349 Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact Biswajeet Guha, Chung-Hsun Lin, Kinyip Phoa, Oleg Golonzka, Ayan Kar +5 more 2025-08-26
12382706 Self-aligned gate endcap (SAGE) architectures with gate-all-around devices Biswajeet Guha, Leonard P. GULER, Dax M. Crum, Tahir Ghani 2025-08-05
12369392 Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates Leonard P. GULER, Michael K. Harper, Biswajeet Guha, Tahir Ghani, Niels Zussblatt +6 more 2025-07-22
12349394 Dielectric isolation layer between a nanowire transistor and a substrate Bruce Beattie, Leonard P. GULER, Biswajeet Guha, Jun Sung Kang 2025-07-01
12328905 Cavity spacer for nanowire transistors Biswajeet Guha, Leonard P. GULER, Souvik Chakrabarty, Jun Sung Kang, Bruce Beattie +1 more 2025-06-10
12328920 Nanoribbon sub-fin isolation by backside Si substrate removal etch selective to source and drain epitaxy Biswajeet Guha, Chung-Hsun Lin, Anand S. Murthy, Tahir Ghani 2025-06-10
12302632 Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process Jun Sung Kang, Kai Loon Cheong, Erica J. Thompson, Biswajeet Guha, Dax M. Crum +2 more 2025-05-13
12294006 Gate-all-around integrated circuit structures having insulator substrate Chung-Hsun Lin, Biswajeet Guha, Stephen M. Cea, Tahir Ghani 2025-05-06
12288789 Gate-all-around integrated circuit structures having devices with source/drain-to-substrate electrical contact Biswajeet Guha, Chung-Hsun Lin, Kinyip Phoa, Oleg Golonzka, Tahir Ghani +5 more 2025-04-29
12272737 Gate-all-around integrated circuit structures having adjacent structures for sub-fin electrical contact Biswajeet Guha, Chung-Hsun Lin, Kinyip Phoa, Oleg Golonzka, Tahir Ghani 2025-04-08
12224350 Self-aligned gate endcap (SAGE) architectures with gate-all-around devices Biswajeet Guha, Leonard P. GULER, Dax M. Crum, Tahir Ghani 2025-02-11
12166031 Substrate-less electrostatic discharge (ESD) integrated circuit structures Biswajeet Guha, Brian J. Greene, Daniel Schulman, Chung-Hsun Lin, Curtis Tsai +1 more 2024-12-10 $13,394,000
12068314 Fabrication of gate-all-around integrated circuit structures having adjacent island structures Leonard P. GULER, Biswajeet Guha, Martin Weiss, Apratim Dhar, William T. BLANTON +7 more 2024-08-20 $20,163,000
12014959 Integrated nanowire and nanoribbon patterning in transistor manufacture Leonard P. GULER, Biswajeet Guha, Mark Armstrong, Tahir Ghani 2024-06-18 $26,452,000
11990472 Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates Leonard P. GULER, Michael K. Harper, Biswajeet Guha, Tahir Ghani, Niels Zussblatt +6 more 2024-05-21 $18,840,000
11929396 Cavity spacer for nanowire transistors Biswajeet Guha, Leonard P. GULER, Souvik Chakrabarty, Jun Sung Kang, Bruce Beattie +1 more 2024-03-12 $37,196,000
11908856 Gate-all-around integrated circuit structures having devices with source/drain-to-substrate electrical contact Biswajeet Guha, Chung-Hsun Lin, Kinyip Phoa, Oleg Golonzka, Tahir Ghani +5 more 2024-02-20 $26,968,000
11901458 Dielectric isolation layer between a nanowire transistor and a substrate Bruce Beattie, Leonard P. GULER, Biswajeet Guha, Jun Sung Kang 2024-02-13 $18,546,000
11894368 Gate-all-around integrated circuit structures fabricated using alternate etch selective material Sudipto Naskar, Biswajeet Guha, Bruce Beattie, Tahir Ghani 2024-02-06 $35,892,000
11869973 Nanowire transistor structure and method of shaping Erica J. Thompson, Aditya Kasukurti, Jun Sung Kang, Kai Loon Cheong, Biswajeet Guha +1 more 2024-01-09 $30,329,000
11869891 Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process Jun Sung Kang, Kai Loon Cheong, Erica J. Thompson, Biswajeet Guha, Dax M. Crum +2 more 2024-01-09 $30,329,000
11855223 Self-aligned gate endcap (SAGE) architectures with gate-all-around devices Biswajeet Guha, Leonard P. GULER, Dax M. Crum, Tahir Ghani 2023-12-26 $39,948,000
11837641 Gate-all-around integrated circuit structures having adjacent deep via substrate contacts for sub-fin electrical contact Biswajeet Guha, Chung-Hsun Lin, Kinyip Phoa, Oleg Golonzka, Tahir Ghani +5 more 2023-12-05 $33,749,000