Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Anand S. Murthy — 348 Patents

Intel: 337 patents #16 of 30,777Top 1%
DPDaedalus Prime: 5 patents #1 of 21Top 5%
Sony: 4 patents #9,005 of 25,231Top 40%
TRTahoe Research: 2 patents #16 of 215Top 8%
Portland, OR: #9 of 9,213 inventorsTop 1%
Oregon: #17 of 28,073 inventorsTop 1%
Overall (All Time): #909 of 4,157,543Top 1%
348 Patents All Time
Anand S. Murthy has been granted 348 US patents while listed as an inventor at Intel. The first was granted in 2001 and the most recent in December 2025. Anand S. Murthy ranks #909 of 4,157,543 US inventors in our database (top 0.02%). Patent records list Anand S. Murthy in Portland, OR, US.

Issued Patents All Time

Showing 1–25 of 348 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12506127 Package architecture of photonic system with vertically stacked dies having planarized edges Sagar Suthram, Ravindranath V. Mahajan, Debendra Mallik, Omkar G. Karhade, Wilfred Gomes +4 more 2025-12-23
12484272 Source or drain structures with relatively high germanium content Cory Bomberger, Biswajeet Guha, Anupama Bowonder, Tahir Ghani 2025-11-25
12484266 Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers Glenn A. Glass, Biswajeet Guha, Dax M. Crum, Patrick H. Keys, Tahir Ghani +2 more 2025-11-25
12471334 Integrated circuit devices with angled transistors formed based on angled wafers Abhishek Sharma, Tahir Ghani, Wilfred Gomes, Sagar Suthram 2025-11-11
12471362 Integrated circuit structures having ultra-high conductivity global routing Abhishek Sharma, Tahir Ghani, Sagar Suthram, Pushkar Ranade, Wilfred Gomes +2 more 2025-11-11
12451420 Staircase-based metal-insulator-metal (MIM) capacitors Prashant Majhi 2025-10-21
12439640 Reduced contact resistivity with PMOS germanium and silicon doped with boron gate all around transistors Cory Bomberger, Rushabh Shah, Kenneth A. Cook, Anupama Bowonder 2025-10-07
12439669 Co-deposition of titanium and silicon for improved silicon germanium source and drain contacts Debaleena Nandi, Chi Choi, Gilbert Dewey, Harold W. Kennel, Omair Saadat +4 more 2025-10-07
12432964 Co-integrated gallium nitride (GaN) and complementary metal oxide semiconductor (CMOS) integrated circuit technology Glenn A. Glass, Robert Ehlert, Han Wui Then, Marko Radosavljevic, Nicole K. Thomas +1 more 2025-09-30
12426342 Low germanium, high boron silicon rich capping layer for PMOS contact resistance thermal stability Debaleena Nandi, Cory Bomberger, Gilbert Dewey, Mauro J. Kobrinsky, Rushabh SHAH +6 more 2025-09-23
12419091 Source electrode and drain electrode protection for nanowire transistors Karthik Jambunathan, Biswajeet Guha, Tahir Ghani 2025-09-16
12414366 Co-integration of high voltage (HV) and low voltage (LV) transistor structures, using channel height and spacing modulation Prashant Majhi, Glenn A. Glass, Rushabh SHAH, Susmita Ghose 2025-09-09
12402387 Integrated circuit structures including a titanium silicide material Dan S. LAVRIC, Glenn A. Glass, Thomas T. TROEGER, Suresh Vishwanath, Jitendra Kumar Jha +2 more 2025-08-26
12388011 Top gate recessed channel CMOS thin film transistor and methods of fabrication Gilbert Dewey, Ryan Keech, Cory Bomberger, Cheng-Ying Huang, Ashish Agrawal +1 more 2025-08-12
12363967 Integration methods to fabricate internal spacers for nanowire devices Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Mark Armstrong, Rafael Rios +2 more 2025-07-15
12349420 Device, method and system to provide a stressed channel of a transistor Rishabh Mehandru, Stephen M. Cea, Tahir Ghani 2025-07-01
12342611 Source or drain structures with vertical trenches Ryan Keech, Nicholas G. Minutillo, Aaron A. Budrevich, Peter Wells 2025-06-24
12342574 Contact resistance reduction in transistor devices with metallization on both sides Koustav Ganguly, Ryan Keech, Subrina RAFIQUE, Glenn A. Glass, Ehren Mannebach +2 more 2025-06-24
12328927 Low resistance and reduced reactivity approaches for fabricating contacts and the resulting structures Gilbert Dewey, Nazila Haratipour, Siddharth Chouksey, Arnab Sen Gupta, Christopher J. Jezewski +2 more 2025-06-10
12328920 Nanoribbon sub-fin isolation by backside Si substrate removal etch selective to source and drain epitaxy William Hsu, Biswajeet Guha, Chung-Hsun Lin, Tahir Ghani 2025-06-10
12294027 Semiconductor device having doped epitaxial region and its methods of fabrication Daniel B. Aubertine, Tahir Ghani, Abhijit Jayant Pethe 2025-05-06
12288808 High aspect ratio source or drain structures with abrupt dopant profile Ryan Keech, Nicholas G. Minutillo, Suresh Vishwanath, Mohammad HASAN, Biswajeet Guha +1 more 2025-04-29
12288803 Transistor with isolation below source and drain Willy Rachmady, Cheng-Ying Huang, Matthew V. Metz, Nicholas G. Minutillo, Sean T. Ma +3 more 2025-04-29
12272727 Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures Cory Bomberger, Susmita Ghose, Siddharth Chouksey 2025-04-08
12266570 Self-aligned interconnect structures and methods of fabrication Kimin Jun, Souvik Ghosh, Willy Rachmady, Ashish Agrawal, Siddharth Chouksey +5 more 2025-04-01