Issued Patents All Time
Showing 25 most recent of 340 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12432964 | Co-integrated gallium nitride (GaN) and complementary metal oxide semiconductor (CMOS) integrated circuit technology | Glenn A. Glass, Robert Ehlert, Han Wui Then, Marko Radosavljevic, Nicole K. Thomas +1 more | 2025-09-30 |
| 12426342 | Low germanium, high boron silicon rich capping layer for PMOS contact resistance thermal stability | Debaleena Nandi, Cory Bomberger, Gilbert Dewey, Mauro J. Kobrinsky, Rushabh SHAH +6 more | 2025-09-23 |
| 12419091 | Source electrode and drain electrode protection for nanowire transistors | Karthik Jambunathan, Biswajeet Guha, Tahir Ghani | 2025-09-16 |
| 12414366 | Co-integration of high voltage (HV) and low voltage (LV) transistor structures, using channel height and spacing modulation | Prashant Majhi, Glenn A. Glass, Rushabh SHAH, Susmita Ghose | 2025-09-09 |
| 12402387 | Integrated circuit structures including a titanium silicide material | Dan S. LAVRIC, Glenn A. Glass, Thomas T. TROEGER, Suresh Vishwanath, Jitendra Kumar Jha +2 more | 2025-08-26 |
| 12388011 | Top gate recessed channel CMOS thin film transistor and methods of fabrication | Gilbert Dewey, Ryan Keech, Cory Bomberger, Cheng-Ying Huang, Ashish Agrawal +1 more | 2025-08-12 |
| 12363967 | Integration methods to fabricate internal spacers for nanowire devices | Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Mark Armstrong, Rafael Rios +2 more | 2025-07-15 |
| 12349420 | Device, method and system to provide a stressed channel of a transistor | Rishabh Mehandru, Stephen M. Cea, Tahir Ghani | 2025-07-01 |
| 12342574 | Contact resistance reduction in transistor devices with metallization on both sides | Koustav Ganguly, Ryan Keech, Subrina RAFIQUE, Glenn A. Glass, Ehren Mannebach +2 more | 2025-06-24 |
| 12342611 | Source or drain structures with vertical trenches | Ryan Keech, Nicholas G. Minutillo, Aaron A. Budrevich, Peter Wells | 2025-06-24 |
| 12328920 | Nanoribbon sub-fin isolation by backside Si substrate removal etch selective to source and drain epitaxy | William Hsu, Biswajeet Guha, Chung-Hsun Lin, Tahir Ghani | 2025-06-10 |
| 12328927 | Low resistance and reduced reactivity approaches for fabricating contacts and the resulting structures | Gilbert Dewey, Nazila Haratipour, Siddharth Chouksey, Arnab Sen Gupta, Christopher J. Jezewski +2 more | 2025-06-10 |
| 12294027 | Semiconductor device having doped epitaxial region and its methods of fabrication | Daniel B. Aubertine, Tahir Ghani, Abhijit Jayant Pethe | 2025-05-06 |
| 12288803 | Transistor with isolation below source and drain | Willy Rachmady, Cheng-Ying Huang, Matthew V. Metz, Nicholas G. Minutillo, Sean T. Ma +3 more | 2025-04-29 |
| 12288808 | High aspect ratio source or drain structures with abrupt dopant profile | Ryan Keech, Nicholas G. Minutillo, Suresh Vishwanath, Mohammad HASAN, Biswajeet Guha +1 more | 2025-04-29 |
| 12272727 | Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures | Cory Bomberger, Susmita Ghose, Siddharth Chouksey | 2025-04-08 |
| 12266570 | Self-aligned interconnect structures and methods of fabrication | Kimin Jun, Souvik Ghosh, Willy Rachmady, Ashish Agrawal, Siddharth Chouksey +5 more | 2025-04-01 |
| 12255234 | Integrated circuit structures having germanium-based channels | Siddharth Chouksey, Glenn A. Glass, Harold W. Kennel, Jack T. Kavalieros, Tahir Ghani +2 more | 2025-03-18 |
| 12237420 | Fin smoothing and integrated circuit structures resulting therefrom | Cory Bomberger, Tahir Ghani, Anupama Bowonder | 2025-02-25 |
| 12206027 | Gate-all-around integrated circuit structures having nanowires with tight vertical spacing | Glenn A. Glass, Biswajeet Guha, Tahir Ghani, Susmita Ghose, Zachary Geiger | 2025-01-21 |
| 12170319 | Dual contact process with stacked metal layers | Kevin T. Cook, Gilbert Dewey, Nazila Haratipour, Ralph T. Troeger, Christopher J. Jezewski +1 more | 2024-12-17 |
| 12166124 | Gate-all-around integrated circuit structures having germanium-doped nanoribbon channel structures | Ryan Murray Hickey, Glenn A. Glass, Rushabh SHAH, Ju H. Nam | 2024-12-10 |
| 12159901 | Gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs | Cory Bomberger, Mark Bohr, Tahir Ghani, Biswajeet Guha | 2024-12-03 |
| 12148751 | Use of a placeholder for backside contact formation for transistor arrangements | Andy Wei, Mauro J. Kobrinsky, Guillaume Bouche | 2024-11-19 |
| 12119387 | Low resistance approaches for fabricating contacts and the resulting structures | Gilbert Dewey, Nazila Haratipour, Siddharth Chouksey, Jack T. Kavalieros, Jitendra Kumar Jha +6 more | 2024-10-15 |