AP

Abhijit Jayant Pethe

IN Intel: 19 patents #2,136 of 30,777Top 7%
SO Sony: 4 patents #8,966 of 25,231Top 40%
Overall (All Time): #178,262 of 4,157,543Top 5%
23
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12363967 Integration methods to fabricate internal spacers for nanowire devices Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Anand S. Murthy, Mark Armstrong +2 more 2025-07-15
12294027 Semiconductor device having doped epitaxial region and its methods of fabrication Anand S. Murthy, Daniel B. Aubertine, Tahir Ghani 2025-05-06
12278144 Gate contact structure over active gate and method to fabricate same Tahir Ghani, Mark Bohr, Clair Webb, Harry Gomez, Annalisa Cappellani 2025-04-15
11908934 Semiconductor device having doped epitaxial region and its methods of fabrication Anand S. Murthy, Daniel Bourne Aubertine, Tahir Ghani 2024-02-20
11869939 Integration methods to fabricate internal spacers for nanowire devices Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Anand S. Murthy, Mark Armstrong +2 more 2024-01-09
11302777 Integration methods to fabricate internal spacers for nanowire devices Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Anand S. Murthy, Mark Armstrong +2 more 2022-04-12
11004739 Gate contact structure over active gate and method to fabricate same Tahir Ghani, Mark Bohr, Clair Webb, Harry Gomez, Annalisa Cappellani 2021-05-11
10957796 Semiconductor device having doped epitaxial region and its methods of fabrication Anand S. Murthy, Daniel Bourne Aubertine, Tahir Ghani 2021-03-23
10847631 Gate-all-around (GAA) transistors with nanowires on an isolation pedestal Annalisa Cappellani, Tahir Ghani, Harry Gomez 2020-11-24
10804357 Integration methods to fabricate internal spacers for nanowire devices Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Anand S. Murthy, Mark Armstrong +2 more 2020-10-13
10580860 Integration methods to fabricate internal spacers for nanowire devices Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Anand S. Murthy, Mark Armstrong +2 more 2020-03-03
10283589 Integration methods to fabricate internal spacers for nanowire devices Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Anand S. Murthy, Mark Armstrong +2 more 2019-05-07
10229981 Gate-all-around (GAA) transistor with stacked nanowires on locally isolated substrate Annalisa Cappellani, Tahir Ghani, Harry Gomez 2019-03-12
10192783 Gate contact structure over active gate and method to fabricate same Tahir Ghani, Mark Bohr, Clair Webb, Harry Gomez, Annalisa Cappellani 2019-01-29
10121856 Integration methods to fabricate internal spacers for nanowire devices Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Anand S. Murthy, Mark Armstrong +2 more 2018-11-06
9859368 Integration methods to fabricate internal spacers for nanowire devices Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Anand S. Murthy, Mark Armstrong +2 more 2018-01-02
9484272 Methods for fabricating strained gate-all-around semiconductor devices by fin oxidation using an undercut etch-stop layer Annalisa Cappellani, Tahir Ghani, Harry Gomez 2016-11-01
9484447 Integration methods to fabricate internal spacers for nanowire devices Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Anand S. Murthy, Mark Armstrong +2 more 2016-11-01
9472399 Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates Annalisa Cappellani, Pragyansri Pathi, Bruce Beattie 2016-10-18
9461143 Gate contact structure over active gate and method to fabricate same Tahir Ghani, Mark Bohr, Clair Webb, Harry Gomez, Annalisa Cappellani 2016-10-04
9041106 Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates Annalisa Cappellani, Pragyansri Pathi, Bruce Beattie 2015-05-26
8735869 Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates Annalisa Cappellani, Tahir Ghani, Harry Gomez 2014-05-27
8598003 Semiconductor device having doped epitaxial region and its methods of fabrication Anand S. Murtthy, Daniel Bourne Aubertine, Tahir Ghani 2013-12-03