Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12278144 | Gate contact structure over active gate and method to fabricate same | Abhijit Jayant Pethe, Tahir Ghani, Mark Bohr, Harry Gomez, Annalisa Cappellani | 2025-04-15 |
| 11004739 | Gate contact structure over active gate and method to fabricate same | Abhijit Jayant Pethe, Tahir Ghani, Mark Bohr, Harry Gomez, Annalisa Cappellani | 2021-05-11 |
| 10192783 | Gate contact structure over active gate and method to fabricate same | Abhijit Jayant Pethe, Tahir Ghani, Mark Bohr, Harry Gomez, Annalisa Cappellani | 2019-01-29 |
| 9496486 | Perpendicular spin transfer torque memory (STTM) device having offset cells and method to form same | Brian S. Doyle, David L. Kencke, Charles C. Kuo, Uday Shah, Kaan Oguz +2 more | 2016-11-15 |
| 9461143 | Gate contact structure over active gate and method to fabricate same | Abhijit Jayant Pethe, Tahir Ghani, Mark Bohr, Harry Gomez, Annalisa Cappellani | 2016-10-04 |
| 9105839 | Perpendicular spin transfer torque memory (STTM) device having offset cells and method to form same | Brian S. Doyle, David L. Kencke, Charles C. Kuo, Uday Shah, Kaan Oguz +2 more | 2015-08-11 |
| 8786040 | Perpendicular spin transfer torque memory (STTM) device having offset cells and method to form same | Brian S. Doyle, David L. Kencke, Charles C. Kuo, Uday Shah, Kaan Oguz +2 more | 2014-07-22 |
| 6762464 | N-p butting connections on SOI substrates | Mark Bohr | 2004-07-13 |
| 5430595 | Electrostatic discharge protection circuit | Glen R. Wagner, Jeffrey E. Smith, Jose Maiz, William M. Holt | 1995-07-04 |
| 5293603 | Cache subsystem for microprocessor based computer system with synchronous and asynchronous data path | Peter D. MacWilliams, Robert L. Farrell | 1994-03-08 |
| 5228134 | Cache memory integrated circuit for use with a synchronous central processor bus and an asynchronous memory bus | Peter D. MacWilliams, Robert L. Farrell | 1993-07-13 |