Issued Patents All Time
Showing 25 most recent of 89 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12363967 | Integration methods to fabricate internal spacers for nanowire devices | Seiyon Kim, Tahir Ghani, Anand S. Murthy, Mark Armstrong, Rafael Rios +2 more | 2025-07-15 |
| 12142634 | Silicon and silicon germanium nanowire structures | Seiyon Kim, Rafael Rios, Stephen M. Cea, Martin D. Giles, Annalisa Cappellani +3 more | 2024-11-12 |
| 12125916 | Nanowire structures having non-discrete source and drain regions | Stephen M. Cea, Annalisa Cappellani, Martin D. Giles, Rafael Rios, Seiyon Kim | 2024-10-22 |
| 12046637 | Nanowire transistor fabrication with hardmask layers | Seung Hoon Sung, Seiyon Kim, Willy Rachmady, Jack T. Kavalieros | 2024-07-23 |
| 11996129 | Semiconductor circuits and devices based on low-energy consumption semiconductor structures exhibiting multi-valued magnetoelectric spin hall effect | Darrell G. Schlom, Mostafizur Rahman, John Heron | 2024-05-28 |
| 11869939 | Integration methods to fabricate internal spacers for nanowire devices | Seiyon Kim, Tahir Ghani, Anand S. Murthy, Mark Armstrong, Rafael Rios +2 more | 2024-01-09 |
| 11677003 | Nanowire transistor fabrication with hardmask layers | Seung Hoon Sung, Seiyon Kim, Willy Rachmady, Jack T. Kavalieros | 2023-06-13 |
| 11581406 | Method of fabricating CMOS FinFETs by selectively etching a strained SiGe layer | Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Anand S. Murthy, Glenn A. Glass +1 more | 2023-02-14 |
| 11552197 | Nanowire structures having non-discrete source and drain regions | Stephen M. Cea, Annalisa Cappellani, Martin D. Giles, Rafael Rios, Seiyon Kim | 2023-01-10 |
| 11302777 | Integration methods to fabricate internal spacers for nanowire devices | Seiyon Kim, Tahir Ghani, Anand S. Murthy, Mark Armstrong, Rafael Rios +2 more | 2022-04-12 |
| 11195919 | Method of fabricating a semiconductor device with strained SiGe fins and a Si cladding layer | Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Anand S. Murthy, Glenn A. Glass +1 more | 2021-12-07 |
| 11139400 | Non-planar semiconductor device having hybrid geometry-based active region | Seiyon Kim, Rafael Rios, Fahmida Ferdousi | 2021-10-05 |
| 11024714 | Nanowire transistor fabrication with hardmask layers | Seung Hoon Sung, Seiyon Kim, Willy Rachmady, Jack T. Kavalieros | 2021-06-01 |
| 10991799 | Silicon and silicon germanium nanowire structures | Seiyon Kim, Rafael Rios, Stephen M. Cea, Martin D. Giles, Annalisa Cappellani +3 more | 2021-04-27 |
| 10825752 | Integrated thermoelectric cooling | Lei Jiang, Edwin B. Ramayya, Daniel Pantuso, Rafael Rios, Seiyon Kim | 2020-11-03 |
| 10804357 | Integration methods to fabricate internal spacers for nanowire devices | Seiyon Kim, Tahir Ghani, Anand S. Murthy, Mark Armstrong, Rafael Rios +2 more | 2020-10-13 |
| 10636871 | Silicon and silicon germanium nanowire structures | Seiyon Kim, Rafael Rios, Stephen M. Cea, Martin D. Giles, Annalisa Cappellani +3 more | 2020-04-28 |
| 10593804 | Non-planar semiconductor device having hybrid geometry-based active region | Seiyon Kim, Rafael Rios, Fahmida Ferdousi | 2020-03-17 |
| 10586868 | Non-planar semiconductor device having hybrid geometry-based active region | Seiyon Kim, Rafael Rios, Fahmida Ferdousi | 2020-03-10 |
| 10580860 | Integration methods to fabricate internal spacers for nanowire devices | Seiyon Kim, Tahir Ghani, Anand S. Murthy, Mark Armstrong, Rafael Rios +2 more | 2020-03-03 |
| 10580899 | Nanowire structures having non-discrete source and drain regions | Stephen M. Cea, Annalisa Cappellani, Martin D. Giles, Rafael Rios, Seiyon Kim | 2020-03-03 |
| 10535770 | Scaled TFET transistor formed using nanowire with surface termination | Uygar E. Avci, Rafael Rios, Ian A. Young, Justin R. Weber | 2020-01-14 |
| 10424580 | Semiconductor devices having modulated nanowire counts | Annalisa Cappellani, Rafael Rios, Gopinath Bhimarasetti, Tahir Ghani, Seiyon Kim | 2019-09-24 |
| 10283589 | Integration methods to fabricate internal spacers for nanowire devices | Seiyon Kim, Tahir Ghani, Anand S. Murthy, Mark Armstrong, Rafael Rios +2 more | 2019-05-07 |
| 10121856 | Integration methods to fabricate internal spacers for nanowire devices | Seiyon Kim, Tahir Ghani, Anand S. Murthy, Mark Armstrong, Rafael Rios +2 more | 2018-11-06 |