Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11594524 | Fabrication and use of through silicon vias on double sided interconnect device | Brennen Mueller, Patrick Morrow, Kimin Jun, Paul B. Fischer | 2023-02-28 |
| 11251156 | Fabrication and use of through silicon vias on double sided interconnect device | Brennen Mueller, Patrick Morrow, Kimin Jun, Paul B. Fischer | 2022-02-15 |
| 11195719 | Reducing in-plane distortion from wafer to wafer bonding using a dummy wafer | Chytra Pawashe | 2021-12-07 |
| 11171057 | Semiconductor fin design to mitigate fin collapse | Glenn A. Glass, Chytra Pawashe, Anand S. Murthy, Tahir Ghani | 2021-11-09 |
| 11056356 | Fluid viscosity control during wafer bonding | Brennen Mueller, Mauro J. Kobrinsky, Chytra Pawashe, Myra McDonnell | 2021-07-06 |
| 10825752 | Integrated thermoelectric cooling | Lei Jiang, Edwin B. Ramayya, Rafael Rios, Kelin J. Kuhn, Seiyon Kim | 2020-11-03 |
| 10720345 | Wafer to wafer bonding with low wafer distortion | Mauro J. Kobrinsky, Myra McDonnell, Brennen Mueller, Chytra Pawashe, Paul B. Fischer +2 more | 2020-07-21 |
| 10707186 | Compliant layer for wafer to wafer bonding | Mauro J. Kobrinsky, Jasmeet S. Chawla, Stefan Meister, Myra McDonnell, Chytra Pawashe | 2020-07-07 |
| 9691716 | Techniques for enhancing fracture resistance of interconnects | Christopher J. Jezewski, Mauro J. Kobrinsky, Siddharth B. Bhingarde, Michael P. O'Day | 2017-06-27 |
| 9343411 | Techniques for enhancing fracture resistance of interconnects | Christopher J. Jezewski, Mauro J. Kobrinsky, Siddharth B. Bhingarde, Michael P. O'Day | 2016-05-17 |
| 6646340 | Thermally coupling electrically decoupling cooling device for integrated circuits | Timothy L. Deeter, Thomas Marieb, Daniel James Murray, Sarangapani Sista | 2003-11-11 |
| 6525419 | Thermally coupling electrically decoupling cooling device for integrated circuits | Timothy L. Deeter, Thomas Marieb, Daniel James Murray, Sarangapani Sista | 2003-02-25 |