Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12394716 | Integrated circuit interconnect structures with graphene cap | Carl Naylor, Matthew V. Metz, Sean King, Ramanan V. Chebiam, Mauro J. Kobrinsky +5 more | 2025-08-19 |
| 12322699 | Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches | Christopher J. Jezewski | 2025-06-03 |
| 11380617 | Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches | Christopher J. Jezewski | 2022-07-05 |
| 11107908 | Transistors with metal source and drain contacts including a Heusler alloy | Sasikanth Manipatruni, Anurag Chaudhry, Dmitri E. Nikonov, Christopher J. Wiegand, Kanwaljit Singh +2 more | 2021-08-31 |
| 11069609 | Techniques for forming vias and other interconnects for integrated circuit structures | Sasikanth Manipatruni, Chia-Ching Lin, Dmitri E. Nikonov, Ian A. Young, Robert L. Bristol | 2021-07-20 |
| 11056593 | Semiconductor devices with metal contacts including crystalline alloys | Sasikanth Manipatruni, Dmitri E. Nikonov, Uygar E. Avci, Christopher J. Wiegand, Anurag Chaudhry +1 more | 2021-07-06 |
| 10971394 | Maskless air gap to prevent via punch through | Manish Chandhok, Todd R. Younkin, Eungnak Han, Marie Krysak, Hui Jae Yoo +1 more | 2021-04-06 |
| 10957844 | Magneto-electric spin orbit (MESO) structures having functional oxide vias | Sasikanth Manipatruni, Robert L. Bristol, Chia-Ching Lin, Dmitri E. Nikonov, Ian A. Young | 2021-03-23 |
| 10707186 | Compliant layer for wafer to wafer bonding | Mauro J. Kobrinsky, Stefan Meister, Myra McDonnell, Chytra Pawashe, Daniel Pantuso | 2020-07-07 |
| 10546772 | Self-aligned via below subtractively patterned interconnect | Manish Chandhok, Richard E. Schenker, Hui Jae Yoo, Kevin Lin, Stephanie A. Bojarski +3 more | 2020-01-28 |
| 10497613 | Microelectronic conductive routes and methods of making the same | Rami Hourani, Mauro J. Kobrinsky, Florian Gstrein, Scott B. Clendenning, Jeanette M. Roberts | 2019-12-03 |
| 10256141 | Maskless air gap to prevent via punch through | Manish Chandhok, Todd R. Younkin, Eungnak Han, Marie Krysak, Hui Jae Yoo +1 more | 2019-04-09 |
| 10109583 | Method for creating alternate hardmask cap interconnect structure with increased overlay margin | Robert L. Bristol, Manish Chandhok, Florian Gstrein, Eungnak Han, Rami Hourani +3 more | 2018-10-23 |
| 10032643 | Method and structure to contact tight pitch conductive layers with guided vias using alternating hardmasks and encapsulating etchstop liner scheme | Ruth A. Brain, Richard E. Schenker, Kanwal Jit Singh, Alan M. Myers | 2018-07-24 |
| 9911694 | Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches | Christopher J. Jezewski | 2018-03-06 |
| 9548269 | Diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects | Alan M. Myers, Kanwal Jit Singh, Robert L. Bristol | 2017-01-17 |
| 9385082 | Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches | Christopher J. Jezewski | 2016-07-05 |
| 9379010 | Methods for forming interconnect layers having tight pitch interconnect structures | Christopher J. Jezewski, Kanwal Jit Singh, Alan M. Myers, Elliot N. Tan, Richard E. Schenker | 2016-06-28 |
| 9209077 | Diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects | Alan M. Myers, Kanwal Jit Singh, Robert L. Bristol | 2015-12-08 |
| 9054164 | Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches | Christopher J. Jezewski | 2015-06-09 |