Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
JC

Jasmeet S. Chawla — 20 Patents

Intel: 19 patents #2,167 of 30,777Top 8%
TRTahoe Research: 1 patents #81 of 215Top 40%
Hillsboro, OR: #220 of 2,365 inventorsTop 10%
Oregon: #2,168 of 28,073 inventorsTop 8%
Overall (All Time): #214,803 of 4,157,543Top 6%
20 Patents All Time
Jasmeet S. Chawla has been granted 20 US patents while listed as an inventor at Intel. The first was granted in 2015 and the most recent in August 2025. Jasmeet S. Chawla ranks #214,803 of 4,157,543 US inventors in our database (top 5.2%). Patent records list Jasmeet S. Chawla in Hillsboro, OR, US.

Patents per Year

Patents granted per year, 2015 to 2025Bar chart with a peak of 5 patents in 2021.peak 52015: 2 patents20152016: 2 patents20162017: 1 patents20172018: 3 patents20182019: 2 patents20192020: 2 patents20202021: 5 patents20212022: 1 patents20222025: 2 patents2025

Issued Patents All Time

Showing 1–20 of 20 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12394716 Integrated circuit interconnect structures with graphene cap Carl Naylor, Matthew V. Metz, Sean King, Ramanan V. Chebiam, Mauro J. Kobrinsky +5 more 2025-08-19
12322699 Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches Christopher J. Jezewski 2025-06-03
11380617 Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches Christopher J. Jezewski 2022-07-05 $18,093,000
11107908 Transistors with metal source and drain contacts including a Heusler alloy Sasikanth Manipatruni, Anurag Chaudhry, Dmitri E. Nikonov, Christopher J. Wiegand, Kanwaljit Singh +2 more 2021-08-31 $22,590,000
11069609 Techniques for forming vias and other interconnects for integrated circuit structures Sasikanth Manipatruni, Chia-Ching Lin, Dmitri E. Nikonov, Ian A. Young, Robert L. Bristol 2021-07-20 $44,320,000
11056593 Semiconductor devices with metal contacts including crystalline alloys Sasikanth Manipatruni, Dmitri E. Nikonov, Uygar E. Avci, Christopher J. Wiegand, Anurag Chaudhry +1 more 2021-07-06 $31,309,000
10971394 Maskless air gap to prevent via punch through Manish Chandhok, Todd R. Younkin, Eungnak Han, Marie Krysak, Hui Jae Yoo +1 more 2021-04-06 $36,336,000
10957844 Magneto-electric spin orbit (MESO) structures having functional oxide vias Sasikanth Manipatruni, Robert L. Bristol, Chia-Ching Lin, Dmitri E. Nikonov, Ian A. Young 2021-03-23 $29,278,000
10707186 Compliant layer for wafer to wafer bonding Mauro J. Kobrinsky, Stefan Meister, Myra McDonnell, Chytra Pawashe, Daniel Pantuso 2020-07-07 $29,601,000
10546772 Self-aligned via below subtractively patterned interconnect Manish Chandhok, Richard E. Schenker, Hui Jae Yoo, Kevin Lin, Stephanie A. Bojarski +3 more 2020-01-28 $38,246,000
10497613 Microelectronic conductive routes and methods of making the same Rami Hourani, Mauro J. Kobrinsky, Florian Gstrein, Scott B. Clendenning, Jeanette M. Roberts 2019-12-03 $19,496,000
10256141 Maskless air gap to prevent via punch through Manish Chandhok, Todd R. Younkin, Eungnak Han, Marie Krysak, Hui Jae Yoo +1 more 2019-04-09 $21,845,000
10109583 Method for creating alternate hardmask cap interconnect structure with increased overlay margin Robert L. Bristol, Manish Chandhok, Florian Gstrein, Eungnak Han, Rami Hourani +3 more 2018-10-23 $21,867,000
10032643 Method and structure to contact tight pitch conductive layers with guided vias using alternating hardmasks and encapsulating etchstop liner scheme Ruth A. Brain, Richard E. Schenker, Kanwal Jit Singh, Alan M. Myers 2018-07-24 $23,531,000
9911694 Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches Christopher J. Jezewski 2018-03-06 $18,859,000
9548269 Diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects Alan M. Myers, Kanwal Jit Singh, Robert L. Bristol 2017-01-17 $15,866,000
9385082 Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches Christopher J. Jezewski 2016-07-05 $9,080,000
9379010 Methods for forming interconnect layers having tight pitch interconnect structures Christopher J. Jezewski, Kanwal Jit Singh, Alan M. Myers, Elliot N. Tan, Richard E. Schenker 2016-06-28 $11,945,000
9209077 Diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects Alan M. Myers, Kanwal Jit Singh, Robert L. Bristol 2015-12-08 $12,754,000
9054164 Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches Christopher J. Jezewski 2015-06-09 $16,785,000