Issued Patents All Time
Showing 25 most recent of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12382721 | Integrated circuit structures having cut metal gates with dielectric spacer fill | Leonard P. GULER, Chanaka D. Munasinghe, Makram ABD EL QADER, Marie T. Conte, Saurabh Morarka +5 more | 2025-08-05 |
| 12278204 | Pattern decomposition lithography techniques | Charles H. Wallace, Hossam A. Abdallah, Swaminathan Sivakumar, Oleg Golonzka, Robert M. Bigwood | 2025-04-15 |
| 12249541 | Vertical edge blocking (VEB) technique for increasing patterning process margin | Leonard P. GULER, Chul-Hyun Lim, Paul A. Nyhus, Charles H. Wallace | 2025-03-11 |
| 12218052 | Advanced lithography and self-assembled devices | Richard E. Schenker, Robert L. Bristol, Kevin Lin, Florian Gstrein, James M. Blackwell +6 more | 2025-02-04 |
| 12148734 | Transistors, memory cells, and arrangements thereof | Sarah Atanasov, Abhishek A. Sharma, Bernhard Sell, Chieh-Jen Ku, Hui Jae Yoo +4 more | 2024-11-19 |
| 12150297 | Thin film transistors having a backside channel contact for high density memory | Noriyuki Sato, Sarah Atanasov, Abhishek A. Sharma, Bernhard Sell, Chieh-Jen Ku +6 more | 2024-11-19 |
| 12114479 | Three-dimensional memory arrays with layer selector transistors | Wilfred Gomes, Mauro J. Kobrinsky, Abhishek A. Sharma, Rajesh Kumar, Kinyip Phoa +2 more | 2024-10-08 |
| 12080781 | Fabrication of thin film fin transistor structure | Noriyuki Sato, Sarah Atanasov, Abhishek A. Sharma, Bernhard Sell, Chieh-Jen Ku +6 more | 2024-09-03 |
| 11950407 | Memory architecture with shared bitline at back-end-of-line | Juan G. Alzate Vinasco, Travis W. Lajoie, Abhishek A. Sharma, Kimberly Pierce, Yu-Jin Chen +3 more | 2024-04-02 |
| 11888043 | Contact over active gate structures with conductive gate taps for advanced integrated circuit structure fabrication | — | 2024-01-30 |
| 11854787 | Advanced lithography and self-assembled devices | Richard E. Schenker, Robert L. Bristol, Kevin Lin, Florian Gstrein, James M. Blackwell +6 more | 2023-12-26 |
| 11594448 | Vertical edge blocking (VEB) technique for increasing patterning process margin | Leonard P. GULER, Chul-Hyun Lim, Paul A. Nyhus, Charles H. Wallace | 2023-02-28 |
| 11581412 | Contact over active gate structures with conductive gate taps for advanced integrated circuit structure fabrication | — | 2023-02-14 |
| 11373950 | Advanced lithography and self-assembled devices | Richard E. Schenker, Robert L. Bristol, Kevin Lin, Florian Gstrein, James M. Blackwell +6 more | 2022-06-28 |
| 11189614 | Process etch with reduced loading effect | Leonard P. GULER | 2021-11-30 |
| 11139300 | Three-dimensional memory arrays with layer selector transistors | Wilfred Gomes, Mauro J. Kobrinsky, Abhishek A. Sharma, Rajesh Kumar, Kinyip Phoa +2 more | 2021-10-05 |
| 11107786 | Pattern decomposition lithography techniques | Charles H. Wallace, Hossam A. Abdallah, Swaminathan Sivakumar, Oleg Golonzka, Robert M. Bigwood | 2021-08-31 |
| 11056492 | Dense memory arrays utilizing access transistors with back-side contacts | Wilfred Gomes, Mauro J. Kobrinsky, Szuya S. Liao, Tahir Ghani, Swaminathan Sivakumar +1 more | 2021-07-06 |
| 11056397 | Directional spacer removal for integrated circuit structures | Leonard P. GULER | 2021-07-06 |
| 10892223 | Advanced lithography and self-assembled devices | Richard E. Schenker, Robert L. Bristol, Kevin Lin, Florian Gstrein, James M. Blackwell +6 more | 2021-01-12 |
| 10811351 | Preformed interlayer connections for integrated circuit devices | — | 2020-10-20 |
| 10600678 | Self-aligned isotropic etch of pre-formed vias and plugs for back end of line (BEOL) interconnects | Charles H. Wallace, Paul A. Nyhus, Swaminathan Sivakumar | 2020-03-24 |
| 10490519 | Pattern decomposition lithography techniques | Charles H. Wallace, Hossam A. Abdallah, Swaminathan Sivakumar, Oleg Golonzka, Robert M. Bigwood | 2019-11-26 |
| 10409152 | Pattern decomposition lithography techniques | Charles H. Wallace, Hossam A. Abdallah, Swaminathan Sivakumar, Oleg Golonzka, Robert M. Bigwood | 2019-09-10 |
| 10211088 | Self-aligned isotropic etch of pre-formed vias and plugs for back end of line (BEOL) interconnects | Charles H. Wallace, Paul A. Nyhus, Swaminathan Sivakumar | 2019-02-19 |