Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
CW

Charles H. Wallace — 103 Patents

Intel: 96 patents #226 of 30,777Top 1%
ITInternational Telephone And Telegraph: 3 patents #51 of 507Top 15%
University of California: 3 patents #2,984 of 18,278Top 20%
Portland, OR: #113 of 9,213 inventorsTop 2%
Oregon: #202 of 28,073 inventorsTop 1%
Overall (All Time): #13,706 of 4,157,543Top 1%
103 Patents All Time
Charles H. Wallace has been granted 103 US patents while listed as an inventor at Intel. The first was granted in 1980 and the most recent in December 2025. Charles H. Wallace ranks #13,706 of 4,157,543 US inventors in our database (top 0.33%). Patent records list Charles H. Wallace in Portland, OR, US.

Issued Patents All Time

Showing 1–25 of 103 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12507464 Gate aligned fin cut for advanced integrated circuit structure fabrication Leonard P. GULER, Moh'd A. Hasan, William Hsu, Biswajeet Guha, Tahir Ghani +2 more 2025-12-23
12506075 Epitaxial source/drain back-side device contact structures with wrap around metallization and protective conformal liner Mohit K. HARAN, Leonard P. GULER, Sukru YEMENICIOGLU, Mauro J. Kobrinsky, Tahir Ghani 2025-12-23
12501659 Integrated circuit structures having dielectric anchor void Leonard P. GULER, Tahir Ghani 2025-12-16
12490462 Angled gate or diffusion plugs Leonard P. GULER, Tsai-Shun Chang, Peter P. Sun, Tahir Ghani, Virupaxi Goornavar 2025-12-02
12484281 Topside plugs for epitaxial contact formation Leonard P. GULER, Nikhil Mehta, Krishnamurthy Ganesan, Chanaka D. Munasinghe, Tahir Ghani 2025-11-25
12471349 Contact over active gate structures with uniform and conformal gate insulating cap layers for advanced integrated circuit structure fabrication Leonard P. GULER, Chanaka D. Munasinghe, Tahir Ghani, Krishnamurthy Ganesan 2025-11-11
12471330 Integrated circuit structures having maximized channel sizing Sukru YEMENICIOGLU, Tahir Ghani, Andy Chi-Hung Wei, Leonard P. GULER, Mohit K. HARAN 2025-11-11
12469780 Integrated circuit structure with recessed self-aligned deep boundary via Mohit K. HARAN, Sukru YEMENICIOGLU, Pratik Patel, Leonard P. GULER, Conor P. Puls +2 more 2025-11-11
12453160 Deep etch processing for transistors having varying pitch Leonard P. GULER, Moh'd A. Hasan, Tahir Ghani 2025-10-21
12444685 Backside electrical contact for PMOS epitaxial voltage supply Clifford L. Ong, Zheng Guo, Eirc A. Karl, Smita Shridharan, Mauro J. Kobrinsky +3 more 2025-10-14
12419085 Integrated circuit structures having backside gate tie-down Leonard P. GULER, Mauro J. Kobrinsky, Mohit K. HARAN, Marni Nabors, Tahir Ghani +2 more 2025-09-16
12405526 Extreme ultraviolet lithography patterning with assist features Leonard P. GULER, Tahir Ghani, Hossam A. Abdallah, Dario Farias, Tsuan-Chung CHANG +5 more 2025-09-02
12408422 Integrated circuit structures with backside gate cut or trench contact cut Leonard P. GULER, Tahir Ghani 2025-09-02
12400913 Contact over active gate structures with conductive trench contact taps for advanced integrated circuit structure fabrication Manish Chandhok, Elijah V. Karpov, Mohit K. HARAN, Reken Patel, Gurpreet Singh +5 more 2025-08-26
12382721 Integrated circuit structures having cut metal gates with dielectric spacer fill Leonard P. GULER, Chanaka D. Munasinghe, Makram ABD EL QADER, Marie T. Conte, Saurabh Morarka +5 more 2025-08-05
12364001 Integrated circuit structures with backside gate partial cut or trench contact partial cut Leonard P. GULER, Mohammad HASAN, Tahir Ghani 2025-07-15
12308284 Plug and trench architectures for integrated circuits and methods of manufacture Marvin Young Paik, Hyunsoo Park, Mohit K. HARAN, Alexander F. Kaplan, Ruth A. Brain 2025-05-20
12293913 Directed self-assembly enabled subtractive metal patterning Gurpreet Singh, Richard E. Schenker, Nityan NAIR, Nafees Kabir, Gauri Nabar +7 more 2025-05-06
12278204 Pattern decomposition lithography techniques Hossam A. Abdallah, Elliot N. Tan, Swaminathan Sivakumar, Oleg Golonzka, Robert M. Bigwood 2025-04-15
12266527 Directed self-assembly enabled patterning over metal layers using assisting features Gurpreet Singh, Nityan NAIR, Nafees Kabir, Eungnak Han, Xuanxuan Chen +6 more 2025-04-01
12266708 Integrated circuit structures having dielectric anchor void Leonard P. GULER, Tahir Ghani 2025-04-01
12249577 Cap structure for interconnect dielectrics and methods of fabrication Shashi Vyas, Sudipto Naskar 2025-03-11
12249541 Vertical edge blocking (VEB) technique for increasing patterning process margin Leonard P. GULER, Chul-Hyun Lim, Paul A. Nyhus, Elliot N. Tan 2025-03-11
12237223 Contact over active gate structures using directed self-assembly for advanced integrated circuit structure fabrication Paul A. Nyhus, Manish Chandhok, Mohit K. HARAN, Gurpreet Singh, Eungnak Han +5 more 2025-02-25
12237388 Transistor arrangements with stacked trench contacts and gate straps Andy Wei, Changyok Park, Guillaume Bouche, Hyuk-Ju Ryu, Mohit K. HARAN 2025-02-25