Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Swaminathan Sivakumar — 61 Patents

Intel: 61 patents #470 of 30,777Top 2%
Beaverton, OR: #72 of 3,140 inventorsTop 3%
Oregon: #510 of 28,073 inventorsTop 2%
Overall (All Time): #37,626 of 4,157,543Top 1%
61 Patents All Time
Swaminathan Sivakumar has been granted 61 US patents while listed as an inventor at Intel. The first was granted in 1999 and the most recent in September 2025. Swaminathan Sivakumar ranks #37,626 of 4,157,543 US inventors in our database (top 0.91%). Patent records list Swaminathan Sivakumar in Beaverton, OR, US.

Patents per Year

Patents granted per year, 1999 to 2025Bar chart with a peak of 6 patents in 2023.peak 61999: 1 patents19992005: 3 patents2007: 4 patents20072008: 1 patents2009: 1 patents20092010: 4 patents2011: 3 patents20112013: 2 patents2014: 1 patents20142015: 3 patents2016: 3 patents20162017: 4 patents2019: 5 patents20192020: 2 patents2021: 4 patents20212022: 5 patents2023: 6 patents20232024: 4 patents2025: 5 patents2025

Issued Patents All Time

Showing 1–25 of 61 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12432897 Cooling approaches for stitched dies Abhishek A. Sharma, Wilfred Gomes, Christopher M. Pelto, Mark C. Phillips 2025-09-30
12426316 Method of fabricating integrated circuits with fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric material Leonard P. GULER, Nick Lindert, Biswajeet Guha, Tahir Ghani 2025-09-23
12342612 Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions Leonard P. GULER, Biswajeet Guha, Tahir Ghani 2025-06-24
12278204 Pattern decomposition lithography techniques Charles H. Wallace, Hossam A. Abdallah, Elliot N. Tan, Oleg Golonzka, Robert M. Bigwood 2025-04-15
12211925 Gate-all-around integrated circuit structures having oxide sub-fins Leonard P. GULER, Biswajeet Guha, Tahir Ghani 2025-01-28
12114479 Three-dimensional memory arrays with layer selector transistors Wilfred Gomes, Mauro J. Kobrinsky, Abhishek A. Sharma, Rajesh Kumar, Kinyip Phoa +2 more 2024-10-08 $19,971,000
12033894 Gate aligned contact and method to fabricate same Oleg Golonzka, Charles H. Wallace, Tahir Ghani 2024-07-09 $24,938,000
11972979 1D vertical edge blocking (VEB) via and plug Leonard P. GULER, Michael K. Harper, Suzanne S. Rich, Charles H. Wallace, Curtis W. Ward +4 more 2024-04-30 $26,151,000
11862635 Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions Leonard P. GULER, Biswajeet Guha, Tahir Ghani 2024-01-02 $30,016,000
11756829 Gate aligned contact and method to fabricate same Oleg Golonzka, Charles H. Wallace, Tahir Ghani 2023-09-12 $19,004,000
11749733 FIN shaping using templates and integrated circuit structures resulting therefrom Leonard P. GULER, Biswajeet Guha, Mark Armstrong, William Hsu, Tahir Ghani 2023-09-05 $19,899,000
11742410 Gate-all-around integrated circuit structures having oxide sub-fins Leonard P. GULER, Biswajeet Guha, Tahir Ghani 2023-08-29 $19,273,000
11721580 1D vertical edge blocking (VEB) via and plug Leonard P. GULER, Michael K. Harper, Suzanne S. Rich, Charles H. Wallace, Curtis W. Ward +4 more 2023-08-08 $22,376,000
11715775 Self-aligned gate endcap (SAGE) architectures with gate-all-around devices having epitaxial source or drain structures Leonard P. GULER, Biswajeet Guha, Tahir Ghani 2023-08-01 $26,467,000
11652060 Die interconnection scheme for providing a high yielding process for high performance microprocessors Wilfred Gomes, Mark Bohr, Rajabali M. Koduri, Leonard NEIBERG, Altug Koker 2023-05-16 $11,130,000
11538937 Fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric material Leonard P. GULER, Nick Lindert, Biswajeet Guha, Tahir Ghani 2022-12-27 $12,365,000
11495496 Gate aligned contact and method to fabricate same Oleg Golonzka, Charles H. Wallace, Tahir Ghani 2022-11-08 $15,080,000
11398474 Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions Leonard P. GULER, Biswajeet Guha, Tahir Ghani 2022-07-26 $27,041,000
11355608 Self-aligned gate endcap (SAGE) architectures with gate-all-around devices having epitaxial source or drain structures Leonard P. GULER, Biswajeet Guha, Tahir Ghani 2022-06-07 $12,864,000
11302790 Fin shaping using templates and integrated circuit structures resulting therefrom Leonard P. GULER, Biswajeet Guha, Mark Armstrong, William Hsu, Tahir Ghani 2022-04-12 $16,909,000
11139300 Three-dimensional memory arrays with layer selector transistors Wilfred Gomes, Mauro J. Kobrinsky, Abhishek A. Sharma, Rajesh Kumar, Kinyip Phoa +2 more 2021-10-05 $23,463,000
11107786 Pattern decomposition lithography techniques Charles H. Wallace, Hossam A. Abdallah, Elliot N. Tan, Oleg Golonzka, Robert M. Bigwood 2021-08-31 $22,590,000
11056492 Dense memory arrays utilizing access transistors with back-side contacts Wilfred Gomes, Mauro J. Kobrinsky, Elliot N. Tan, Szuya S. Liao, Tahir Ghani +1 more 2021-07-06 $31,309,000
10910265 Gate aligned contact and method to fabricate same Oleg Golonzka, Charles H. Wallace, Tahir Ghani 2021-02-02 $28,243,000
10607884 Gate aligned contact and method to fabricate same Oleg Golonzka, Charles H. Wallace, Tahir Ghani 2020-03-31 $34,068,000