Issued Patents All Time
Showing 25 most recent of 61 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12432897 | Cooling approaches for stitched dies | Abhishek A. Sharma, Wilfred Gomes, Christopher M. Pelto, Mark C. Phillips | 2025-09-30 |
| 12426316 | Method of fabricating integrated circuits with fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric material | Leonard P. GULER, Nick Lindert, Biswajeet Guha, Tahir Ghani | 2025-09-23 |
| 12342612 | Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions | Leonard P. GULER, Biswajeet Guha, Tahir Ghani | 2025-06-24 |
| 12278204 | Pattern decomposition lithography techniques | Charles H. Wallace, Hossam A. Abdallah, Elliot N. Tan, Oleg Golonzka, Robert M. Bigwood | 2025-04-15 |
| 12211925 | Gate-all-around integrated circuit structures having oxide sub-fins | Leonard P. GULER, Biswajeet Guha, Tahir Ghani | 2025-01-28 |
| 12114479 | Three-dimensional memory arrays with layer selector transistors | Wilfred Gomes, Mauro J. Kobrinsky, Abhishek A. Sharma, Rajesh Kumar, Kinyip Phoa +2 more | 2024-10-08 |
| 12033894 | Gate aligned contact and method to fabricate same | Oleg Golonzka, Charles H. Wallace, Tahir Ghani | 2024-07-09 |
| 11972979 | 1D vertical edge blocking (VEB) via and plug | Leonard P. GULER, Michael K. Harper, Suzanne S. Rich, Charles H. Wallace, Curtis W. Ward +4 more | 2024-04-30 |
| 11862635 | Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions | Leonard P. GULER, Biswajeet Guha, Tahir Ghani | 2024-01-02 |
| 11756829 | Gate aligned contact and method to fabricate same | Oleg Golonzka, Charles H. Wallace, Tahir Ghani | 2023-09-12 |
| 11749733 | FIN shaping using templates and integrated circuit structures resulting therefrom | Leonard P. GULER, Biswajeet Guha, Mark Armstrong, William Hsu, Tahir Ghani | 2023-09-05 |
| 11742410 | Gate-all-around integrated circuit structures having oxide sub-fins | Leonard P. GULER, Biswajeet Guha, Tahir Ghani | 2023-08-29 |
| 11721580 | 1D vertical edge blocking (VEB) via and plug | Leonard P. GULER, Michael K. Harper, Suzanne S. Rich, Charles H. Wallace, Curtis W. Ward +4 more | 2023-08-08 |
| 11715775 | Self-aligned gate endcap (SAGE) architectures with gate-all-around devices having epitaxial source or drain structures | Leonard P. GULER, Biswajeet Guha, Tahir Ghani | 2023-08-01 |
| 11652060 | Die interconnection scheme for providing a high yielding process for high performance microprocessors | Wilfred Gomes, Mark Bohr, Rajabali M. Koduri, Leonard NEIBERG, Altug Koker | 2023-05-16 |
| 11538937 | Fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric material | Leonard P. GULER, Nick Lindert, Biswajeet Guha, Tahir Ghani | 2022-12-27 |
| 11495496 | Gate aligned contact and method to fabricate same | Oleg Golonzka, Charles H. Wallace, Tahir Ghani | 2022-11-08 |
| 11398474 | Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions | Leonard P. GULER, Biswajeet Guha, Tahir Ghani | 2022-07-26 |
| 11355608 | Self-aligned gate endcap (SAGE) architectures with gate-all-around devices having epitaxial source or drain structures | Leonard P. GULER, Biswajeet Guha, Tahir Ghani | 2022-06-07 |
| 11302790 | Fin shaping using templates and integrated circuit structures resulting therefrom | Leonard P. GULER, Biswajeet Guha, Mark Armstrong, William Hsu, Tahir Ghani | 2022-04-12 |
| 11139300 | Three-dimensional memory arrays with layer selector transistors | Wilfred Gomes, Mauro J. Kobrinsky, Abhishek A. Sharma, Rajesh Kumar, Kinyip Phoa +2 more | 2021-10-05 |
| 11107786 | Pattern decomposition lithography techniques | Charles H. Wallace, Hossam A. Abdallah, Elliot N. Tan, Oleg Golonzka, Robert M. Bigwood | 2021-08-31 |
| 11056492 | Dense memory arrays utilizing access transistors with back-side contacts | Wilfred Gomes, Mauro J. Kobrinsky, Elliot N. Tan, Szuya S. Liao, Tahir Ghani +1 more | 2021-07-06 |
| 10910265 | Gate aligned contact and method to fabricate same | Oleg Golonzka, Charles H. Wallace, Tahir Ghani | 2021-02-02 |
| 10607884 | Gate aligned contact and method to fabricate same | Oleg Golonzka, Charles H. Wallace, Tahir Ghani | 2020-03-31 |