Issued Patents All Time
Showing 26–50 of 61 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10600678 | Self-aligned isotropic etch of pre-formed vias and plugs for back end of line (BEOL) interconnects | Charles H. Wallace, Elliot N. Tan, Paul A. Nyhus | 2020-03-24 |
| 10459338 | Exposure activated chemically amplified directed self-assembly (DSA) for back end of line (BEOL) pattern cutting and plugging | Paul A. Nyhus, Eungnak Han, Ernisse Putna | 2019-10-29 |
| 10340185 | Gate aligned contact and method to fabricate same | Oleg Golonzka, Charles H. Wallace, Tahir Ghani | 2019-07-02 |
| 10325814 | Patterning of vertical nanowire transistor channel and gate with directed self assembly | Paul A. Nyhus | 2019-06-18 |
| 10211088 | Self-aligned isotropic etch of pre-formed vias and plugs for back end of line (BEOL) interconnects | Charles H. Wallace, Elliot N. Tan, Paul A. Nyhus | 2019-02-19 |
| 10204830 | Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects | Charles H. Wallace, Paul A. Nyhus, Elliot N. Tan | 2019-02-12 |
| 9793159 | Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects | Charles H. Wallace, Paul A. Nyhus, Elliot N. Tan | 2017-10-17 |
| 9716037 | Gate aligned contact and method to fabricate same | Oleg Golonzka, Charles H. Wallace, Tahir Ghani | 2017-07-25 |
| 9653576 | Patterning of vertical nanowire transistor channel and gate with directed self assembly | Paul A. Nyhus | 2017-05-16 |
| 9625815 | Exposure activated chemically amplified directed self-assembly (DSA) for back end of line (BEOL) pattern cutting and plugging | Paul A. Nyhus, Eungnak Han, Ernisse Putna | 2017-04-18 |
| 9530688 | Directed self assembly of block copolymers to form vias aligned with interconnects | Paul A. Nyhus, Robert L. Bristol | 2016-12-27 |
| 9431518 | Patterning of vertical nanowire transistor channel and gate with directed self assembly | Paul A. Nyhus | 2016-08-30 |
| 9269630 | Patterning of vertical nanowire transistor channel and gate with directed self assembly | Paul A. Nyhus | 2016-02-23 |
| 9224794 | Embedded memory device having MIM capacitor formed in excavated structure | Steven J. Keating, Nick Lindert, Nadia M. Rahhal-Orabi, Brian S. Doyle, Satyarth Suri +2 more | 2015-12-29 |
| 9054215 | Patterning of vertical nanowire transistor channel and gate with directed self assembly | Paul A. Nyhus | 2015-06-09 |
| 8959465 | Techniques for phase tuning for process optimization | Paul A. Nyhus, Shem Ogadhoh, Seongtae Jeong | 2015-02-17 |
| 8860184 | Spacer assisted pitch division lithography | Elliot N. Tan | 2014-10-14 |
| 8519462 | 6F2 DRAM cell | Yih Wang, M. Clair Webb, Nick Lindert, Kevin X. Zhang, Dinesh Somasekhar | 2013-08-27 |
| 8441057 | Embedded memory device having MIM capacitor formed in excavated structure | Steven J. Keating, Nick Lindert, Nadia M. Rahhal-Orabi, Brian S. Doyle, Satyarth Suri +2 more | 2013-05-14 |
| 8013426 | Transistor having raised source/drain self-aligned contacts and method of forming same | — | 2011-09-06 |
| 7981756 | Common plate capacitor array connections, and processes of making same | Nick Lindert, Brian S. Doyle, Dinesh Somasekhar, Christopher J. Jezewski, Kevin X. Zhang +1 more | 2011-07-19 |
| 7927959 | Method of patterning a metal on a vertical sidewall of an excavated feature, method of forming an embedded MIM capacitor using same, and embedded memory device produced thereby | Steven J. Keating, Nick Lindert, Nadia M. Rahhal-Orabi, Brian S. Doyle, Satyarth Suri +2 more | 2011-04-19 |
| 7820550 | Negative tone double patterning method | Paul A. Nyhus, Charles H. Wallace | 2010-10-26 |
| 7816061 | Lithography masks for improved line-end patterning | Richard E. Schenker, Paul A. Nyhus, Sven Henrichs | 2010-10-19 |
| 7755082 | Forming self-aligned nano-electrodes | Valery M. Dubin, Andrew Berlin, Mark Bohr | 2010-07-13 |