{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Intel", "item": "https://www.patentleaderboard.com/company/intel"}, {"@type": "ListItem", "position": 3, "name": "Paul A. Nyhus", "item": "https://www.patentleaderboard.com/inventor/fl:pa_ln:nyhus-1"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
PN

Paul A. Nyhus — 54 Patents

Intel: 54 patents #576 of 30,777Top 2%
Portland, OR: #308 of 9,213 inventorsTop 4%
Oregon: #612 of 28,073 inventorsTop 3%
Overall (All Time): #46,969 of 4,157,543Top 2%
54 Patents All Time
Paul A. Nyhus has been granted 54 US patents while listed as an inventor at Intel. The first was granted in 2006 and the most recent in August 2025. Paul A. Nyhus ranks #46,969 of 4,157,543 US inventors in our database (top 1.1%). Patent records list Paul A. Nyhus in Portland, OR, US.

Patents per Year

Patents granted per year, 2006 to 2025Bar chart with a peak of 7 patents in 2019.peak 72006: 1 patents20062007: 1 patents2008: 1 patents20082009: 1 patents2010: 3 patents20102015: 4 patents2016: 4 patents20162017: 5 patents2019: 7 patents20192020: 4 patents2021: 2 patents20212022: 4 patents2023: 5 patents20232024: 6 patents2025: 6 patents2025

Issued Patents All Time

Showing 1–25 of 54 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12400913 Contact over active gate structures with conductive trench contact taps for advanced integrated circuit structure fabrication Manish Chandhok, Elijah V. Karpov, Mohit K. HARAN, Reken Patel, Charles H. Wallace +5 more 2025-08-26
12293913 Directed self-assembly enabled subtractive metal patterning Gurpreet Singh, Richard E. Schenker, Nityan NAIR, Nafees Kabir, Gauri Nabar +7 more 2025-05-06
12266527 Directed self-assembly enabled patterning over metal layers using assisting features Gurpreet Singh, Nityan NAIR, Nafees Kabir, Eungnak Han, Xuanxuan Chen +6 more 2025-04-01
12249541 Vertical edge blocking (VEB) technique for increasing patterning process margin Leonard P. GULER, Chul-Hyun Lim, Elliot N. Tan, Charles H. Wallace 2025-03-11
12237223 Contact over active gate structures using directed self-assembly for advanced integrated circuit structure fabrication Charles H. Wallace, Manish Chandhok, Mohit K. HARAN, Gurpreet Singh, Eungnak Han +5 more 2025-02-25
12218052 Advanced lithography and self-assembled devices Richard E. Schenker, Robert L. Bristol, Kevin Lin, Florian Gstrein, James M. Blackwell +6 more 2025-02-04
12131991 Self aligned gratings for tight pitch interconnects and methods of fabrication Manish Chandhok, Leonard P. GULER, Gobind Bisht, Jonathan Laib, David Shykind +5 more 2024-10-29 $18,861,000
12131989 Vertical metal splitting using helmets and wrap-around dielectric spacers Leonard P. GULER, Charles H. Wallace 2024-10-29 $18,861,000
12087594 Colored gratings in microelectronic structures Gurpreet Singh, Eungnak Han, Manish Chandhok, Richard E. Schenker, Florian Gstrein +1 more 2024-09-10 $16,964,000
12080639 Contact over active gate structures with metal oxide layers to inhibit shorting Rami Hourani, Manish Chandhok, Richard E. Schenker, Florian Gstrein, Leonard P. GULER +4 more 2024-09-03 $14,017,000
12002678 Gate spacing in integrated circuit structures Charles H. Wallace, Mohit K. HARAN, Gurpreet Singh, Eungnak Han, David Shykind +1 more 2024-06-04 $24,500,000
11972979 1D vertical edge blocking (VEB) via and plug Leonard P. GULER, Michael K. Harper, Suzanne S. Rich, Charles H. Wallace, Curtis W. Ward +4 more 2024-04-30 $26,151,000
11854787 Advanced lithography and self-assembled devices Richard E. Schenker, Robert L. Bristol, Kevin Lin, Florian Gstrein, James M. Blackwell +6 more 2023-12-26 $39,948,000
11721580 1D vertical edge blocking (VEB) via and plug Leonard P. GULER, Michael K. Harper, Suzanne S. Rich, Charles H. Wallace, Curtis W. Ward +4 more 2023-08-08 $22,376,000
11605623 Materials and layout design options for DSA on transition regions over active die Gurpreet Singh, Eungnak Han, Florian Gstrein, Richard E. Schenker 2023-03-14 $29,588,000
11594448 Vertical edge blocking (VEB) technique for increasing patterning process margin Leonard P. GULER, Chul-Hyun Lim, Elliot N. Tan, Charles H. Wallace 2023-02-28 $10,430,000
11545449 Guard ring structure for an integrated circuit Gurpreet Singh 2023-01-03 $15,575,000
11527433 Via and plug architectures for integrated circuit interconnects and methods of manufacture Leonard P. GULER, Charles H. Wallace 2022-12-13 $11,573,000
11417567 Conductive cap-based approaches for conductive via fabrication and structures resulting therefrom Florian Gstrein, Eungnak Han, Rami Hourani, Ruth A. Brain, Manish Chandhok +2 more 2022-08-16 $17,788,000
11373950 Advanced lithography and self-assembled devices Richard E. Schenker, Robert L. Bristol, Kevin Lin, Florian Gstrein, James M. Blackwell +6 more 2022-06-28 $15,065,000
11251117 Self aligned gratings for tight pitch interconnects and methods of fabrication Manish Chandhok, Leonard P. GULER, Gobind Bisht, Jonathan Laib, David Shykind +5 more 2022-02-15 $14,138,000
10991599 Self-aligned via and plug patterning for back end of line (BEOL) interconnects Charles H. Wallace 2021-04-27 $44,593,000
10892223 Advanced lithography and self-assembled devices Richard E. Schenker, Robert L. Bristol, Kevin Lin, Florian Gstrein, James M. Blackwell +6 more 2021-01-12 $55,416,000
10692757 Means to decouple the diffusion and solubility switch mechanisms of photoresists Marie Krysak, Robert L. Bristol, Michael J. Leeson 2020-06-23 $27,746,000
10636700 Metal via processing schemes with via critical dimension (CD) control for back end of line (BEOL) interconnects and the resulting structures Mohit K. HARAN, Charles H. Wallace, Robert M. Bigwood, Deepak S. Rao, Alexander F. Kaplan 2020-04-28 $36,717,000