Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Michael K. Harper — 18 Patents

Intel: 18 patents #2,313 of 30,777Top 8%
Hillsboro, OR: #246 of 2,365 inventorsTop 15%
Oregon: #2,430 of 28,073 inventorsTop 9%
Overall (All Time): #245,716 of 4,157,543Top 6%
18 Patents All Time
Michael K. Harper has been granted 18 US patents while listed as an inventor at Intel. The first was granted in 2011 and the most recent in October 2025. Michael K. Harper ranks #245,716 of 4,157,543 US inventors in our database (top 5.9%). Patent records list Michael K. Harper in Hillsboro, OR, US.

Issued Patents All Time

Showing 1–18 of 18 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12457771 Plug and recess process for dual metal gate on stacked nanoribbon devices Nicole K. Thomas, Leonard P. GULER, Marko Radosavljevic, Thoe Michaelos 2025-10-28
12369392 Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates Leonard P. GULER, William Hsu, Biswajeet Guha, Tahir Ghani, Niels Zussblatt +6 more 2025-07-22
12068314 Fabrication of gate-all-around integrated circuit structures having adjacent island structures Leonard P. GULER, William Hsu, Biswajeet Guha, Martin Weiss, Apratim Dhar +7 more 2024-08-20 $20,163,000
12046652 Plug and recess process for dual metal gate on stacked nanoribbon devices Nicole K. Thomas, Leonard P. GULER, Marko Radosavljevic, Thoe Michaelos 2024-07-23 $20,446,000
11990472 Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates Leonard P. GULER, William Hsu, Biswajeet Guha, Tahir Ghani, Niels Zussblatt +6 more 2024-05-21 $18,840,000
11972979 1D vertical edge blocking (VEB) via and plug Leonard P. GULER, Suzanne S. Rich, Charles H. Wallace, Curtis W. Ward, Richard E. Schenker +4 more 2024-04-30 $26,151,000
11721580 1D vertical edge blocking (VEB) via and plug Leonard P. GULER, Suzanne S. Rich, Charles H. Wallace, Curtis W. Ward, Richard E. Schenker +4 more 2023-08-08 $22,376,000
11594637 Gate-all-around integrated circuit structures having fin stack isolation Leonard P. GULER, Stephen D. Snyder, Biswajeet Guha, William Hsu, Urusa Alaan +4 more 2023-02-28 $10,430,000
11569231 Non-planar transistors with channel regions having varying widths Stephen D. Snyder, Leonard P. GULER, Richard E. Schenker, Sam Sivakumar, Urusa Alaan +2 more 2023-01-31 $11,941,000
9916988 Sacrificial material for stripping masking layers Shakuntala Sundararajan, Nadia M. Rahhal-Orabi, Leonard P. GULER, Ralph T. Troeger 2018-03-13 $24,990,000
9905693 Trigate transistor structure with unrecessed field insulator and thinner electrodes over the field insulator Michael L. Hattendorf, Pragyansri Pathi 2018-02-27 $23,267,000
9768249 Trigate transistor structure with unrecessed field insulator and thinner electrodes over the field insulator Michael L. Hattendorf, Pragyansri Pathi 2017-09-19 $8,005,000
8629039 Substrate fins with different heights Willy Rachmady, Justin S. Sandford 2014-01-14 $22,721,000
8441074 Substrate fins with different heights Willy Rachmady, Justin S. Sandford 2013-05-14 $17,697,000
8377771 Recessed workfunction metal in CMOS transistor gates Willy Rachmady, Brian McIntrye, Subhash M. Joshi 2013-02-19 $11,474,000
8314034 Feature size reduction Elliot N. Tan 2012-11-20 $10,358,000
8193641 Recessed workfunction metal in CMOS transistor gates Willy Rachmady, Brian McIntyre, Subhash M. Joshi 2012-06-05 $18,221,000
7977248 Double patterning with single hard mask Elliot N. Tan, James Jeong 2011-07-12 $25,282,000