Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12369392 | Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates | Leonard P. GULER, William Hsu, Biswajeet Guha, Tahir Ghani, Niels Zussblatt +6 more | 2025-07-22 |
| 12068314 | Fabrication of gate-all-around integrated circuit structures having adjacent island structures | Leonard P. GULER, William Hsu, Biswajeet Guha, Martin Weiss, Apratim Dhar +7 more | 2024-08-20 |
| 12046652 | Plug and recess process for dual metal gate on stacked nanoribbon devices | Nicole K. Thomas, Leonard P. GULER, Marko Radosavljevic, Thoe Michaelos | 2024-07-23 |
| 11990472 | Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates | Leonard P. GULER, William Hsu, Biswajeet Guha, Tahir Ghani, Niels Zussblatt +6 more | 2024-05-21 |
| 11972979 | 1D vertical edge blocking (VEB) via and plug | Leonard P. GULER, Suzanne S. Rich, Charles H. Wallace, Curtis W. Ward, Richard E. Schenker +4 more | 2024-04-30 |
| 11721580 | 1D vertical edge blocking (VEB) via and plug | Leonard P. GULER, Suzanne S. Rich, Charles H. Wallace, Curtis W. Ward, Richard E. Schenker +4 more | 2023-08-08 |
| 11594637 | Gate-all-around integrated circuit structures having fin stack isolation | Leonard P. GULER, Stephen D. Snyder, Biswajeet Guha, William Hsu, Urusa Alaan +4 more | 2023-02-28 |
| 11569231 | Non-planar transistors with channel regions having varying widths | Stephen D. Snyder, Leonard P. GULER, Richard E. Schenker, Sam Sivakumar, Urusa Alaan +2 more | 2023-01-31 |
| 9916988 | Sacrificial material for stripping masking layers | Shakuntala Sundararajan, Nadia M. Rahhal-Orabi, Leonard P. GULER, Ralph T. Troeger | 2018-03-13 |
| 9905693 | Trigate transistor structure with unrecessed field insulator and thinner electrodes over the field insulator | Michael L. Hattendorf, Pragyansri Pathi | 2018-02-27 |
| 9768249 | Trigate transistor structure with unrecessed field insulator and thinner electrodes over the field insulator | Michael L. Hattendorf, Pragyansri Pathi | 2017-09-19 |
| 8629039 | Substrate fins with different heights | Willy Rachmady, Justin S. Sandford | 2014-01-14 |
| 8441074 | Substrate fins with different heights | Willy Rachmady, Justin S. Sandford | 2013-05-14 |
| 8377771 | Recessed workfunction metal in CMOS transistor gates | Willy Rachmady, Brian McIntrye, Subhash M. Joshi | 2013-02-19 |
| 8314034 | Feature size reduction | Elliot N. Tan | 2012-11-20 |
| 8193641 | Recessed workfunction metal in CMOS transistor gates | Willy Rachmady, Brian McIntyre, Subhash M. Joshi | 2012-06-05 |
| 7977248 | Double patterning with single hard mask | Elliot N. Tan, James Jeong | 2011-07-12 |