Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11569231 | Non-planar transistors with channel regions having varying widths | Stephen D. Snyder, Leonard P. GULER, Richard E. Schenker, Michael K. Harper, Urusa Alaan +2 more | 2023-01-31 |
| 7648803 | Diagonal corner-to-corner sub-resolution assist features for photolithography | Charles H. Wallace, Shannon Daviess | 2010-01-19 |
| 7374865 | Methods to pattern contacts using chromeless phase shift masks | Paul A. Nyhus | 2008-05-20 |
| 7179570 | Chromeless phase shift lithography (CPL) masks having features to pattern large area line/space geometries | Paul A. Nyhus | 2007-02-20 |
| 7056645 | Use of chromeless phase shift features to pattern large area line/space geometries | Paul A. Nyhus | 2006-06-06 |
| 6774037 | Method integrating polymeric interlayer dielectric in integrated circuits | Makarem A. Hussein, Ruth A. Brain, Robert Turklot | 2004-08-10 |
| 6649515 | Photoimageable material patterning techniques useful in fabricating conductive lines in circuit structures | Peter K. Moon, Makarem A. Hussein, Alan M. Myers, Charles Recchia, Angelo Kandas | 2003-11-18 |
| 6406995 | Pattern-sensitive deposition for damascene processing | Makarem A. Hussein, Alan M. Myers, Charles Recchia, Angelo Kandas | 2002-06-18 |
| 6384481 | Single step electroplating process for interconnect via fill and metal line patterning | Makarem A. Hussein, Kevin J. Lee | 2002-05-07 |
| 6365529 | Method for patterning dual damascene interconnects using a sacrificial light absorbing material | Makarem A. Hussein | 2002-04-02 |
| 6350670 | Method for making a semiconductor device having a carbon doped oxide insulating layer | Ebrahim Andideh, Larry Wong | 2002-02-26 |
| 6329118 | Method for patterning dual damascene interconnects using a sacrificial light absorbing material | Makarem A. Hussein | 2001-12-11 |
| 6037255 | Method for making integrated circuit having polymer interlayer dielectric | Makarem A. Hussein, Rick Davis | 2000-03-14 |
| 6020266 | Single step electroplating process for interconnect via fill and metal line patterning | Makarem A. Hussein, Kevin J. Lee | 2000-02-01 |