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Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
KL

Kevin J. Lee — 74 Patents

Intel: 43 patents #801 of 30,777Top 3%
Apple: 5 patents #5,490 of 18,612Top 30%
Amazon: 3 patents #5,214 of 19,158Top 30%
SSSift Science: 2 patents #23 of 56Top 45%
GLGlaxo Group Limited: 2 patents #493 of 1,368Top 40%
BCBehavior Tech Computer: 2 patents #20 of 96Top 25%
WCWarner-Lambert Company: 1 patents #930 of 1,610Top 60%
TFThermo Fisher: 1 patents #1,342 of 2,015Top 70%
LOLongyear™: 1 patents #7 of 20Top 35%
SGSosei Group: 1 patents #4 of 18Top 25%
TSMC: 1 patents #8,466 of 12,232Top 70%
CUColumbia University: 1 patents #1,151 of 2,492Top 50%
San Jose, CA: #491 of 32,062 inventorsTop 2%
California: #4,029 of 386,348 inventorsTop 2%
Overall (All Time): #26,215 of 4,157,543Top 1%
74 Patents All Time
Kevin J. Lee has been granted 74 US patents while listed as an inventor at Intel. The first was granted in 1987 and the most recent in August 2025. Kevin J. Lee ranks #26,215 of 4,157,543 US inventors in our database (top 0.63%). Patent records list Kevin J. Lee in San Jose, CA, US.

Patents per Year

Patents granted per year, 1987 to 2025Bar chart with a peak of 6 patents in 2015.peak 61987: 1 patents19871993: 1 patents2000: 4 patents2001: 2 patents20012002: 2 patents2003: 2 patents2004: 2 patents20042005: 1 patents2006: 5 patents2007: 1 patents20072008: 2 patents2009: 4 patents2010: 4 patents20102011: 3 patents2012: 2 patents2013: 1 patents20132014: 5 patents2015: 6 patents2016: 4 patents20162017: 4 patents2018: 2 patents2019: 3 patents20192020: 3 patents2021: 1 patents2022: 3 patents20222023: 1 patents2024: 4 patents2025: 1 patents2025

Issued Patents All Time

Showing 1–25 of 74 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12394158 Content playback based on a path Allessandra E. McGinnis, Connor A. Smith, Jack R. Dashwood, Luis R. Deliz Centeno 2025-08-19
12113948 Systems and methods of managing spatial groups in multi-user communication sessions Connor A. Smith, Willem MATTELAER, Joseph P. Cerra 2024-10-08 $261,024,000
12099695 Systems and methods of managing spatial groups in multi-user communication sessions Connor A. Smith, Willem MATTELAER, Joseph P. Cerra 2024-09-24 $301,193,000
12101197 Temporarily suspending spatial constraints Connor A. Smith, Luis R. Deliz Centeno 2024-09-24 $301,193,000
11989404 Time-based visualization of content anchored in time Allessandra E. McGinnis, Luis R. Deliz Centeno 2024-05-21 $215,899,000
11620653 Systems and methods for configuring and implementing a malicious account testing machine learning model in a machine learning-based digital threat mitigation platform Wei Liu, Hui Wang, Rishabh Kothari, Helen Marushchenko 2023-04-04
11469268 Damascene-based approaches for embedding spin hall MTJ devices into a logic processor and the resulting structures Yih Wang 2022-10-11 $16,542,000
11429974 Systems and methods for configuring and implementing a card testing machine learning model in a machine learning-based digital threat mitigation platform Wei Liu, Hui Wang, Rishabh Kothari, Helen Marushchenko 2022-08-30
11393873 Approaches for embedding spin hall MTJ devices into a logic processor and the resulting structures Yih Wang 2022-07-19 $11,394,000
11037896 Method and apparatus for forming backside die planar devices and saw filter Ruchir Saraswat, Uwe Zillmann, Nicholas P. Cowley, Richard J. Goldman 2021-06-15 $33,380,000
10811595 Techniques for forming logic including integrated spin-transfer torque magnetoresistive random-access memory Oleg Golonzka, Tahir Ghani, Ruth A. Brain, Yih Wang 2020-10-20 $43,271,000
10790263 Integrated circuit die having backside passive components and methods associated therewith 2020-09-29 $31,444,000
10644064 Logic chip including embedded magnetic tunnel junctions Tahir Ghani, Joseph M. Steigerwald, John H. Epple, Yih Wang 2020-05-05 $29,615,000
10455308 Die with integrated microphone device using through-silicon vias (TSVs) Ruchir Saraswat, Uwe Zillmann, Valluri Rao, Tor Lund-Larsen, Nicholas P. Cowley 2019-10-22 $16,310,000
10290598 Method and apparatus for forming backside die planar devices and saw filter Ruchir Saraswat, Uwe Zillmann, Nicholas P. Cowley, Richard J. Goldman 2019-05-14 $24,469,000
10224309 Integrated circuit die having backside passive components and methods associated therewith 2019-03-05 $19,977,000
9997563 Logic chip including embedded magnetic tunnel junctions Tahir Ghani, Joseph M. Steigerwald, John H. Epple, Yih Wang 2018-06-12 $21,622,000
9911689 Through-body-via isolated coaxial capacitor and techniques for forming same Ruchir Saraswat, Uwe Zillmann, Nicholas P. Cowley, Andre Schaefer, Rinkle Jain +1 more 2018-03-06 $18,859,000
9852964 Through-body via formation techniques 2017-12-26 $14,594,000
9721886 Preservation of fine pitch redistribution lines Hiten Kothari, Wayne M. Lytle 2017-08-01 $11,137,000
9716066 Interconnect structure comprising fine pitch backside metal redistribution lines combined with vias James Jeong, Hsiao-Kang Chang, John Muirhead, Adwait Telang, Puneesh Puri +2 more 2017-07-25 $17,281,000
9660181 Logic chip including embedded magnetic tunnel junctions Tahir Ghani, Joseph M. Steigerwald, John H. Epple, Yih Wang 2017-05-23 $7,972,000
9530740 3D interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach Mark Bohr, Andrew W. Yeoh, Christopher M. Pelto, Hiten Kothari, Seshu V. Sattiraju +1 more 2016-12-27 $11,980,000
9489354 Masking content while preserving layout of a webpage Michael W. Nail, Homan Lee 2016-11-08 $53,719,000
9449913 3D interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined with through-silicon vias Mark Bohr, Andrew W. Yeoh, Christopher M. Pelto, Hiten Kothari, Seshu V. Sattiraju +1 more 2016-09-20 $10,814,000