Hiten Kothari — 11 Patents at Intel

Hiten Kothari has been granted 11 US patents while listed as an inventor at Intel. The first was granted in 2008 and the most recent in September 2025. Hiten Kothari ranks #435,149 of 4,157,543 US inventors in our database (top 10.5%). Patent records list Hiten Kothari in Beaverton, OR, US.

Issued Patents All Time

Showing 1–11 of 11 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
12406931	Contact over active gate structures with etch stop layers for advanced integrated circuit structure fabrication	Atul MADHAVAN, Nicholas J. Kybert, Mohit K. HARAN	2025-09-02
12261122	Contact over active gate structures with etch stop layers for advanced integrated circuit structure fabrication	Atul MADHAVAN, Nicholas J. Kybert, Mohit K. HARAN	2025-03-25
11489112	Resistive random access memory device and methods of fabrication	Namrata S. Asuri, Oleg Golonzka, Nathan Strutt, Patrick J. Hentges, Trinh T. Van +6 more	2022-11-01	$18,130,000
11430948	Resistive random access memory device with switching multi-layer stack and methods of fabrication	Timothy E. Glassman, Dragos Seghete, Nathan Strutt, Namrata S. Asuri, Oleg Golonzka +1 more	2022-08-30	$13,077,000
11393754	Contact over active gate structures with etch stop layers for advanced integrated circuit structure fabrication	Atul MADHAVAN, Nicholas J. Kybert, Mohit K. HARAN	2022-07-19	$11,394,000
9818710	Anchored interconnect	Jiho Kang, Carole C. Montarou, Andrew W. Yeoh	2017-11-14	$11,178,000
9721886	Preservation of fine pitch redistribution lines	Kevin J. Lee, Wayne M. Lytle	2017-08-01	$11,137,000
9530740	3D interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach	Kevin J. Lee, Mark Bohr, Andrew W. Yeoh, Christopher M. Pelto, Seshu V. Sattiraju +1 more	2016-12-27	$11,980,000
9449913	3D interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined with through-silicon vias	Kevin J. Lee, Mark Bohr, Andrew W. Yeoh, Christopher M. Pelto, Seshu V. Sattiraju +1 more	2016-09-20	$10,814,000
9142510	3D interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach	Kevin J. Lee, Mark Bohr, Andrew W. Yeoh, Christopher M. Pelto, Seshu V. Sattiraju +1 more	2015-09-22	$9,820,000
7361261	Method of preparing a chiral substrate surface by electrodeposition	Jay A. Switzer, Shuji Nakanishi, Eric W. Bohannan	2008-04-22

Hiten Kothari — 11 Patents

Issued Patents All Time

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