| 12506075 |
Epitaxial source/drain back-side device contact structures with wrap around metallization and protective conformal liner |
Charles H. Wallace, Leonard P. GULER, Sukru YEMENICIOGLU, Mauro J. Kobrinsky, Tahir Ghani |
2025-12-23 |
|
| 12471330 |
Integrated circuit structures having maximized channel sizing |
Sukru YEMENICIOGLU, Tahir Ghani, Andy Chi-Hung Wei, Leonard P. GULER, Charles H. Wallace |
2025-11-11 |
|
| 12469780 |
Integrated circuit structure with recessed self-aligned deep boundary via |
Sukru YEMENICIOGLU, Pratik Patel, Charles H. Wallace, Leonard P. GULER, Conor P. Puls +2 more |
2025-11-11 |
|
| 12419085 |
Integrated circuit structures having backside gate tie-down |
Leonard P. GULER, Mauro J. Kobrinsky, Marni Nabors, Tahir Ghani, Charles H. Wallace +2 more |
2025-09-16 |
|
| 12406931 |
Contact over active gate structures with etch stop layers for advanced integrated circuit structure fabrication |
Atul MADHAVAN, Nicholas J. Kybert, Hiten Kothari |
2025-09-02 |
|
| 12400913 |
Contact over active gate structures with conductive trench contact taps for advanced integrated circuit structure fabrication |
Manish Chandhok, Elijah V. Karpov, Reken Patel, Charles H. Wallace, Gurpreet Singh +5 more |
2025-08-26 |
|
| 12382721 |
Integrated circuit structures having cut metal gates with dielectric spacer fill |
Leonard P. GULER, Chanaka D. Munasinghe, Makram ABD EL QADER, Marie T. Conte, Saurabh Morarka +5 more |
2025-08-05 |
|
| 12369392 |
Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates |
Leonard P. GULER, Michael K. Harper, William Hsu, Biswajeet Guha, Tahir Ghani +6 more |
2025-07-22 |
|
| 12310060 |
Gate-all-around integrated circuit structures having uniform threshold voltages and tight gate endcap tolerances |
Dan S. LAVRIC, Dax M. Crum, David J. TOWNER, Orb Acton, Jitendra Kumar Jha +3 more |
2025-05-20 |
|
| 12308284 |
Plug and trench architectures for integrated circuits and methods of manufacture |
Charles H. Wallace, Marvin Young Paik, Hyunsoo Park, Alexander F. Kaplan, Ruth A. Brain |
2025-05-20 |
|
| 12261122 |
Contact over active gate structures with etch stop layers for advanced integrated circuit structure fabrication |
Atul MADHAVAN, Nicholas J. Kybert, Hiten Kothari |
2025-03-25 |
|
| 12237223 |
Contact over active gate structures using directed self-assembly for advanced integrated circuit structure fabrication |
Paul A. Nyhus, Charles H. Wallace, Manish Chandhok, Gurpreet Singh, Eungnak Han +5 more |
2025-02-25 |
|
| 12237388 |
Transistor arrangements with stacked trench contacts and gate straps |
Andy Wei, Changyok Park, Guillaume Bouche, Hyuk-Ju Ryu, Charles H. Wallace |
2025-02-25 |
|
| 12199161 |
Contact over active gate structures with tapered gate or trench contact for advanced integrated circuit structure fabrication |
Charles H. Wallace, Andy Wei |
2025-01-14 |
|
| 12154855 |
Self-aligned patterning with colored blocking and structures resulting therefrom |
Reken Patel, Richard E. Schenker, Charles H. Wallace |
2024-11-26 |
$26,820,000 |
| 12080639 |
Contact over active gate structures with metal oxide layers to inhibit shorting |
Rami Hourani, Manish Chandhok, Richard E. Schenker, Florian Gstrein, Leonard P. GULER +4 more |
2024-09-03 |
$14,017,000 |
| 12002678 |
Gate spacing in integrated circuit structures |
Charles H. Wallace, Paul A. Nyhus, Gurpreet Singh, Eungnak Han, David Shykind +1 more |
2024-06-04 |
$24,500,000 |
| 11990472 |
Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates |
Leonard P. GULER, Michael K. Harper, William Hsu, Biswajeet Guha, Tahir Ghani +6 more |
2024-05-21 |
$18,840,000 |
| 11972979 |
1D vertical edge blocking (VEB) via and plug |
Leonard P. GULER, Michael K. Harper, Suzanne S. Rich, Charles H. Wallace, Curtis W. Ward +4 more |
2024-04-30 |
$26,151,000 |
| 11721580 |
1D vertical edge blocking (VEB) via and plug |
Leonard P. GULER, Michael K. Harper, Suzanne S. Rich, Charles H. Wallace, Curtis W. Ward +4 more |
2023-08-08 |
$22,376,000 |
| 11664274 |
Method to repair edge placement errors in a semiconductor device |
Charles H. Wallace, Gopinath Bhimarasetti |
2023-05-30 |
$16,378,000 |
| 11652045 |
Via contact patterning method to increase edge placement error margin |
Daniel James Bahr, Deepak S. Rao, Marvin Young Paik, Seungdo An, Debashish Basu +6 more |
2023-05-16 |
$11,130,000 |
| 11393754 |
Contact over active gate structures with etch stop layers for advanced integrated circuit structure fabrication |
Atul MADHAVAN, Nicholas J. Kybert, Hiten Kothari |
2022-07-19 |
$11,394,000 |
| 11211324 |
Via contact patterning method to increase edge placement error margin |
Daniel James Bahr, Deepak S. Rao, Marvin Young Paik, Seungdo An, Debashish Basu +6 more |
2021-12-28 |
$27,770,000 |
| 11171043 |
Plug and trench architectures for integrated circuits and methods of manufacture |
Charles H. Wallace, Marvin Young Paik, Hyunsoo Park, Alexander F. Kaplan, Ruth A. Brain |
2021-11-09 |
$28,241,000 |
