Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
RP

Reken Patel — 11 Patents

Intel: 10 patents #4,072 of 30,777Top 15%
Portland, OR: #1,615 of 9,213 inventorsTop 20%
Oregon: #3,944 of 28,073 inventorsTop 15%
Overall (All Time): #435,149 of 4,157,543Top 15%
11 Patents All Time
Reken Patel has been granted 11 US patents while listed as an inventor at Intel. The first was granted in 2018 and the most recent in August 2025. Reken Patel ranks #435,149 of 4,157,543 US inventors in our database (top 10.5%). Patent records list Reken Patel in Portland, OR, US.

Patents per Year

Patents granted per year, 2018 to 2025Bar chart with a peak of 4 patents in 2024.peak 42018: 1 patents20182021: 2 patents20212023: 2 patents20232024: 4 patents20242025: 2 patents2025

Issued Patents All Time

Showing 1–11 of 11 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12400913 Contact over active gate structures with conductive trench contact taps for advanced integrated circuit structure fabrication Manish Chandhok, Elijah V. Karpov, Mohit K. HARAN, Charles H. Wallace, Gurpreet Singh +5 more 2025-08-26
12369392 Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates Leonard P. GULER, Michael K. Harper, William Hsu, Biswajeet Guha, Tahir Ghani +6 more 2025-07-22
12154855 Self-aligned patterning with colored blocking and structures resulting therefrom Mohit K. HARAN, Richard E. Schenker, Charles H. Wallace 2024-11-26 $26,820,000
12080639 Contact over active gate structures with metal oxide layers to inhibit shorting Rami Hourani, Manish Chandhok, Richard E. Schenker, Florian Gstrein, Leonard P. GULER +4 more 2024-09-03 $14,017,000
11990472 Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates Leonard P. GULER, Michael K. Harper, William Hsu, Biswajeet Guha, Tahir Ghani +6 more 2024-05-21 $18,840,000
11972979 1D vertical edge blocking (VEB) via and plug Leonard P. GULER, Michael K. Harper, Suzanne S. Rich, Charles H. Wallace, Curtis W. Ward +4 more 2024-04-30 $26,151,000
11721580 1D vertical edge blocking (VEB) via and plug Leonard P. GULER, Michael K. Harper, Suzanne S. Rich, Charles H. Wallace, Curtis W. Ward +4 more 2023-08-08 $22,376,000
11652045 Via contact patterning method to increase edge placement error margin Mohit K. HARAN, Daniel James Bahr, Deepak S. Rao, Marvin Young Paik, Seungdo An +6 more 2023-05-16 $11,130,000
11211324 Via contact patterning method to increase edge placement error margin Mohit K. HARAN, Daniel James Bahr, Deepak S. Rao, Marvin Young Paik, Seungdo An +6 more 2021-12-28 $27,770,000
11145541 Conductive via and metal line end fabrication and structures resulting therefrom Charles H. Wallace, Hyunsoo Park, Mohit K. HARAN, Debashish Basu, Curtis W. Ward +1 more 2021-10-12 $32,982,000
10038213 Group IV metal or semiconductor nanowire fabric Brian A. Korgel, Damon A. Smith, Vincent Holmberg, Paul Thurk 2018-07-31