Issued Patents All Time
Showing 25 most recent of 97 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12426316 | Method of fabricating integrated circuits with fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric material | Leonard P. GULER, Nick Lindert, Swaminathan Sivakumar, Tahir Ghani | 2025-09-23 |
| 12419091 | Source electrode and drain electrode protection for nanowire transistors | Karthik Jambunathan, Anand S. Murthy, Tahir Ghani | 2025-09-16 |
| 12412611 | Time decoupled write operations for non-linear polar material based memory | Rajeev Kumar Dokania, Pramod Kolar, Mustansir Yunus Mukadam, Darshak Doshi, Tanay Gosavi +3 more | 2025-09-09 |
| 12402349 | Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact | William Hsu, Chung-Hsun Lin, Kinyip Phoa, Oleg Golonzka, Ayan Kar +5 more | 2025-08-26 |
| 12382706 | Self-aligned gate endcap (SAGE) architectures with gate-all-around devices | William Hsu, Leonard P. GULER, Dax M. Crum, Tahir Ghani | 2025-08-05 |
| 12369393 | Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up approach | Dax M. Crum, Leonard P. GULER, Tahir Ghani | 2025-07-22 |
| 12369392 | Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates | Leonard P. GULER, Michael K. Harper, William Hsu, Tahir Ghani, Niels Zussblatt +6 more | 2025-07-22 |
| 12364002 | Integrated circuit structures having metal gates with tapered plugs | Mohammad HASAN, Oleg Golonzka, Leonard P. GULER, Leah Shoer, Daniel G. Ouellette +2 more | 2025-07-15 |
| 12349394 | Dielectric isolation layer between a nanowire transistor and a substrate | Bruce Beattie, Leonard P. GULER, Jun Sung Kang, William Hsu | 2025-07-01 |
| 12342612 | Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions | Leonard P. GULER, Tahir Ghani, Swaminathan Sivakumar | 2025-06-24 |
| 12336278 | Gate-all-around integrated circuit structures having high mobility | Roza Kotlyar, Rishabh Mehandru, Stephen M. Cea, Dax M. Crum, Tahir Ghani | 2025-06-17 |
| 12328905 | Cavity spacer for nanowire transistors | William Hsu, Leonard P. GULER, Souvik Chakrabarty, Jun Sung Kang, Bruce Beattie +1 more | 2025-06-10 |
| 12328947 | Substrate-less silicon controlled rectifier (SCR) integrated circuit structures | Rui Ma, Kalyan C. Kolluru, Nicholas A. Thomson, Ayan Kar, Benjamin Orr +3 more | 2025-06-10 |
| 12328920 | Nanoribbon sub-fin isolation by backside Si substrate removal etch selective to source and drain epitaxy | William Hsu, Chung-Hsun Lin, Anand S. Murthy, Tahir Ghani | 2025-06-10 |
| 12317590 | Substrate-free integrated circuit structures | Brian J. Greene, Avyaya Jayanthinarasimham, Ayan Kar, Benjamin Orr, Chung-Hsun Lin +9 more | 2025-05-27 |
| 12302632 | Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process | Jun Sung Kang, Kai Loon Cheong, Erica J. Thompson, William Hsu, Dax M. Crum +2 more | 2025-05-13 |
| 12294006 | Gate-all-around integrated circuit structures having insulator substrate | Chung-Hsun Lin, William Hsu, Stephen M. Cea, Tahir Ghani | 2025-05-06 |
| 12288789 | Gate-all-around integrated circuit structures having devices with source/drain-to-substrate electrical contact | William Hsu, Chung-Hsun Lin, Kinyip Phoa, Oleg Golonzka, Tahir Ghani +5 more | 2025-04-29 |
| 12288808 | High aspect ratio source or drain structures with abrupt dopant profile | Ryan Keech, Anand S. Murthy, Nicholas G. Minutillo, Suresh Vishwanath, Mohammad HASAN +1 more | 2025-04-29 |
| 12272737 | Gate-all-around integrated circuit structures having adjacent structures for sub-fin electrical contact | William Hsu, Chung-Hsun Lin, Kinyip Phoa, Oleg Golonzka, Tahir Ghani | 2025-04-08 |
| 12230721 | Gate-all-around integrated circuit structures having asymmetric source and drain contact structures | Mauro J. Kobrinsky, Tahir Ghani | 2025-02-18 |
| 12230717 | Integrated circuit structures having partitioned source or drain contact structures | Mauro J. Kobrinsky, Stephanie A. Bojarski, Babita Dhayal, Tahir Ghani | 2025-02-18 |
| 12224350 | Self-aligned gate endcap (SAGE) architectures with gate-all-around devices | William Hsu, Leonard P. GULER, Dax M. Crum, Tahir Ghani | 2025-02-11 |
| 12211925 | Gate-all-around integrated circuit structures having oxide sub-fins | Leonard P. GULER, Tahir Ghani, Swaminathan Sivakumar | 2025-01-28 |
| 12206027 | Gate-all-around integrated circuit structures having nanowires with tight vertical spacing | Glenn A. Glass, Anand S. Murthy, Tahir Ghani, Susmita Ghose, Zachary Geiger | 2025-01-21 |