Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12412611 | Time decoupled write operations for non-linear polar material based memory | Rajeev Kumar Dokania, Pramod Kolar, Mustansir Yunus Mukadam, Biswajeet Guha, Tanay Gosavi +3 more | 2025-09-09 |
| 12308838 | Exclusive-or logic gate with non-linear input capacitors | Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2025-05-20 |
| 12147747 | Area oriented logic synthesis | Ikenna Odinaka, Sasikanth Manipatruni, Rajeev Kumar Dokania, Amrita Mathuriya | 2024-11-19 |
| 11967954 | Majority or minority logic gate with non-linear input capacitors without reset | Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2024-04-23 |
| 11922105 | Computer-aided design tool for minimum gate count initialization | Ikenna Odinaka, Sasikanth Manipatruni, Rajeev Kumar Dokania, Amrita Mathuriya | 2024-03-05 |
| 11861279 | Computer-aided design tool for inverter minimization | Ikenna Odinaka, Sasikanth Manipatruni, Rajeev Kumar Dokania, Amrita Mathuriya | 2024-01-02 |
| 11861278 | Computer-aided design tool for gate pruning | Ikenna Odinaka, Sasikanth Manipatruni, Rajeev Kumar Dokania, Amrita Mathuriya | 2024-01-02 |
| 11853666 | Computer-aided design tool for wide-input logic initialization | Ikenna Odinaka, Sasikanth Manipatruni, Rajeev Kumar Dokania, Amrita Mathuriya | 2023-12-26 |
| 11816408 | Computer-aided design tool for majority or minority inverter graph synthesis | Ikenna Odinaka, Sasikanth Manipatruni, Rajeev Kumar Dokania, Amrita Mathuriya | 2023-11-14 |
| 11809801 | Computer-aided design tool for circuit logic initialization | Ikenna Odinaka, Sasikanth Manipatruni, Rajeev Kumar Dokania, Amrita Mathuriya | 2023-11-07 |
| 11757452 | OR-and-invert logic based on a mix of majority or minority logic gate with non-linear input capacitors and other logic gates | Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2023-09-12 |
| 11750197 | AND-OR-invert logic based on a mix of majority OR minority logic gate with non-linear input capacitors and other logic gates | Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2023-09-05 |
| 11748537 | Computer-aided design tool for logic synthesis of a mix of CMOS gates and majority and minority logic circuits | Ikenna Odinaka, Sasikanth Manipatruni, Rajeev Kumar Dokania, Amrita Mathuriya | 2023-09-05 |