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USPTO Patent Rankings Data through Dec 31, 2025
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Ikenna Odinaka — 76 Patents

KCKepler Computing: 70 patents #7 of 42Top 20%
Durham, NC: #31 of 4,103 inventorsTop 1%
North Carolina: #281 of 45,564 inventorsTop 1%
Overall (All Time): #24,882 of 4,157,543Top 1%
76 Patents All Time
Ikenna Odinaka has been granted 76 US patents while listed as an inventor at Kepler Computing. The first was granted in 2022 and the most recent in November 2025. Ikenna Odinaka ranks #24,882 of 4,157,543 US inventors in our database (top 0.60%). Patent records list Ikenna Odinaka in Durham, NC, US.

Issued Patents All Time

Showing 1–25 of 76 patents

Patent #TitleCo-InventorsDate
12481481 Asynchronous carry-ripple adder with majority or minority gates Amrita Mathuriya, Nabil Imam, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni 2025-11-25
12451888 Ripple carry adder with ferroelectric or paraelectric wide-input minority or majority gates Amrita Mathuriya, Rajeev Kumar Dokania, Rafael Rios, Sasikanth Manipatruni 2025-10-21
12445134 Diode connected non-linear input capacitors based majority gate Amrita Mathuriya, Rafael Rios, Dmitri E. Nikonov, Biswajeet Guha, Rajeev Kumar Dokania +1 more 2025-10-14
12436739 Non-linear polar material based low power multiplier with transmission-gate based reset mechanism Amrita Mathuriya, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni 2025-10-07
12411657 Asynchronous full-adder with majority or minority gates to generate carry-out true output Nabil Imam, Amrita Mathuriya, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni 2025-09-09
12405768 Asynchronous full-adder with majority or minority gates to generate carry-out false output Nabil Imam, Amrita Mathuriya, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni 2025-09-02
12379898 Asynchronous full-adder with majority or minority gates to generate sum false output Nabil Imam, Amrita Mathuriya, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni 2025-08-05
12374377 Ferroelectric or paraelectric wide-input minority or majority gate based low power adder Amrita Mathuriya, Rajeev Kumar Dokania, Rafael Rios, Sasikanth Manipatruni 2025-07-29
12334923 Multi-cycle reset mechanism for a chain of majority gates having non-linear polar material Amrita Mathuriya, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni 2025-06-17
12334918 Stacked non-planar capacitors based multi-function linear threshold gate with input based adaptive threshold Amrita Mathuriya, Rafael Rios, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni 2025-06-17
12322743 Multi-function threshold gate with input based adaptive threshold and with stacked non-planar paraelectric capacitors Amrita Mathuriya, Rafael Rios, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni 2025-06-03
12316319 Multi-function linear threshold gate with input based adaptive threshold Amrita Mathuriya, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni 2025-05-27
12308838 Exclusive-or logic gate with non-linear input capacitors Amrita Mathuriya, Rafael Rios, Darshak Doshi, Rajeev Kumar Dokania, Sasikanth Manipatruni 2025-05-20
12308836 Method of adjusting threshold of a linear capacitive-input circuit Amrita Mathuriya, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni 2025-05-20
12294370 Area optimized ferroelectric or paraelectric based low power multiplier Amrita Mathuriya, Rajeev Kumar Dokania, Rafael Rios, Sasikanth Manipatruni 2025-05-06
12289104 Ferroelectric or paraelectric based low power multiplier array Amrita Mathuriya, Rajeev Kumar Dokania, Rafael Rios, Sasikanth Manipatruni 2025-04-29
12283955 Majority or minority based low power checkerboard carry save multiplier with inverted multiplier cells Amrita Mathuriya, Rajeev Kumar Dokania, Rafael Rios, Sasikanth Manipatruni 2025-04-22
12218045 Stacked planar capacitors based multi-function linear threshold gate with input based adaptive threshold Amrita Mathuriya, Rafael Rios, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni 2025-02-04
12212321 Non-linear polar material based flip-flop Amrita Mathuriya, Rajeev Kumar Dokania, Rafael Rios, Sasikanth Manipatruni 2025-01-28
12155383 Reset mechanism for an adder or a multiplier having paraelectric material Amrita Mathuriya, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni 2024-11-26
12147747 Area oriented logic synthesis Sasikanth Manipatruni, Darshak Doshi, Rajeev Kumar Dokania, Amrita Mathuriya 2024-11-19
12126339 Apparatus with selectable majority gate and combinational logic gate outputs Sasikanth Manipatruni, Rafael Rios, Robert Menezes, Rajeev Kumar Dokania, Ramamoorthy Ramesh +1 more 2024-10-22
12118327 Ripple carry adder with inverted ferroelectric or paraelectric based adders Amrita Mathuriya, Rajeev Kumar Dokania, Rafael Rios, Sasikanth Manipatruni 2024-10-15
12118330 Low power multiplier with non-linear polar material based reset mechanism with sequential reset Amrita Mathuriya, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni 2024-10-15
12107579 Method for conditioning majority or minority gate Rajeev Kumar Dokania, Amrita Mathuriya, Rafael Rios, Robert Menezes, Ramamoorthy Ramesh +1 more 2024-10-01