Issued Patents All Time
Showing 25 most recent of 53 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12412611 | Time decoupled write operations for non-linear polar material based memory | Rajeev Kumar Dokania, Pramod Kolar, Mustansir Yunus Mukadam, Darshak Doshi, Biswajeet Guha +3 more | 2025-09-09 |
| 12347476 | Apparatus and method to improve sensing noise margin in a non-linear polar material based bit-cell | Ahmad Tavakoli, Rajeev Kumar Dokania, Mustansir Yunus Mukadam, Amrita Mathuriya, Tanay Gosavi +2 more | 2025-07-01 |
| 12334127 | Non-linear polar material based multi-capacitor high density bit-cell | Rajeev Kumar Dokania, Mustansir Yunus Mukadam, Erik Unterborn, Pramod Kolar, Amrita Mathuriya +3 more | 2025-06-17 |
| 12334918 | Stacked non-planar capacitors based multi-function linear threshold gate with input based adaptive threshold | Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2025-06-17 |
| 12322743 | Multi-function threshold gate with input based adaptive threshold and with stacked non-planar paraelectric capacitors | Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2025-06-03 |
| 12283571 | Ultra high-bandwidth artificial intelligence (AI) processor with DRAM under the processor | Rajeev Kumar Dokania, Sasikanth Manipatruni, Amrita Mathuriya | 2025-04-22 |
| 12243797 | 3D stack of split graphics processing logic dies | Amrita Mathuriya, Christopher B. Wilkerson, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2025-03-04 |
| 12218045 | Stacked planar capacitors based multi-function linear threshold gate with input based adaptive threshold | Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2025-02-04 |
| 12171103 | Multi-input threshold gate having stacked and folded non-planar capacitors | Rajeev Kumar Dokania, Amrita Mathuriya, Tanay Gosavi, Noriyuki Sato, Sasikanth Manipatruni | 2024-12-17 |
| 12166011 | Method of forming an artificial intelligence processor with three-dimensional stacked memory | Rajeev Kumar Dokania, Sasikanth Manipatruni, Amrita Mathuriya | 2024-12-10 |
| 12147941 | Iterative monetization of precursor in process development of non-linear polar material and devices | Sasikanth Manipatruni, Niloy Mukherjee, Noriyuki Sato, Tanay Gosavi, Somilkumar J. Rathi +3 more | 2024-11-19 |
| 12108609 | Memory bit-cell with stacked and folded planar capacitors | Rajeev Kumar Dokania, Amrita Mathuriya, Tanay Gosavi, Noriyuki Sato, Sasikanth Manipatruni | 2024-10-01 |
| 12096638 | One transistor and N memory element based memory bit-cell having stacked and folded planar memory elements with and without offset | Rajeev Kumar Dokania, Amrita Mathuriya, Tanay Gosavi, Noriyuki Sato, Sasikanth Manipatruni | 2024-09-17 |
| 12087730 | Multi-input threshold gate having stacked and folded planar capacitors with and without offset | Rajeev Kumar Dokania, Amrita Mathuriya, Tanay Gosavi, Noriyuki Sato, Sasikanth Manipatruni | 2024-09-10 |
| 12086410 | Ferroelectric memory chiplet in a multi-dimensional packaging with I/O switch embedded in a substrate or interposer | Amrita Mathuriya, Christopher B. Wilkerson, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2024-09-10 |
| 12079475 | Ferroelectric memory chiplet in a multi-dimensional packaging | Amrita Mathuriya, Christopher B. Wilkerson, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2024-09-03 |
| 12062584 | Iterative method of multilayer stack development for device applications | Sasikanth Manipatruni, Niloy Mukherjee, Noriyuki Sato, Tanay Gosavi, Mauricio Manfrini +4 more | 2024-08-13 |
| 12041785 | 1TnC memory bit-cell having stacked and folded non-planar capacitors | Rajeev Kumar Dokania, Amrita Mathuriya, Tanay Gosavi, Noriyuki Sato, Sasikanth Manipatruni | 2024-07-16 |
| 12026034 | Method and apparatus for heuristic-based power gating of non-CMOS logic and CMOS based logic | Amrita Mathuriya, Christopher B. Wilkerson, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2024-07-02 |
| 12019492 | Method and apparatus for managing power in a multi-dimensional packaging | Amrita Mathuriya, Christopher B. Wilkerson, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2024-06-25 |
| 12001266 | Method and apparatus for managing power of ferroelectric or paraelectric logic and CMOS based logic | Amrita Mathuriya, Christopher B. Wilkerson, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2024-06-04 |
| 11997853 | 1TnC memory bit-cell having stacked and folded planar capacitors with lateral offset | Rajeev Kumar Dokania, Amrita Mathuriya, Tanay Gosavi, Noriyuki Sato, Sasikanth Manipatruni | 2024-05-28 |
| 11985831 | Multi-function threshold gate with input based adaptive threshold and with stacked non-planar ferroelectric capacitors | Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2024-05-14 |
| 11978762 | Planar capacitors with non-linear polar material staggered on a shared electrode | Rajeev Kumar Dokania, Amrita Mathuriya, Tanay Gosavi, Noriyuki Sato, Sasikanth Manipatruni | 2024-05-07 |
| 11955153 | Multi-element gain memory bit-cell having stacked and folded planar memory elements with and without offset | Rajeev Kumar Dokania, Amrita Mathuriya, Tanay Gosavi, Noriyuki Sato, Sasikanth Manipatruni | 2024-04-09 |