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USPTO Patent Rankings Data through Dec 31, 2025
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Robert Menezes — 29 Patents

KCKepler Computing: 29 patents #13 of 42Top 35%
Portland, OR: #637 of 9,213 inventorsTop 7%
Oregon: #1,376 of 28,073 inventorsTop 5%
Overall (All Time): #127,851 of 4,157,543Top 4%
29 Patents All Time
Robert Menezes has been granted 29 US patents while listed as an inventor at Kepler Computing. The first was granted in 2021 and the most recent in May 2025. Robert Menezes ranks #127,851 of 4,157,543 US inventors in our database (top 3.1%). Patent records list Robert Menezes in Portland, OR, US.

Issued Patents All Time

Showing 1–25 of 29 patents

Patent #TitleCo-InventorsDate
12308837 Multiplier with non-linear polar material Sasikanth Manipatruni, Yuan-Sheng Fang, Rajeev Kumar Dokania, Gaurav Thareja, Amrita Mathuriya +1 more 2025-05-20
12126339 Apparatus with selectable majority gate and combinational logic gate outputs Sasikanth Manipatruni, Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Ramamoorthy Ramesh +1 more 2024-10-22
12107579 Method for conditioning majority or minority gate Rajeev Kumar Dokania, Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Ramamoorthy Ramesh +1 more 2024-10-01
12088297 Majority gate based low power ferroelectric based adder with reset mechanism Sasikanth Manipatruni, Yuan-Sheng Fang, Rajeev Kumar Dokania, Gaurav Thareja, Ramamoorthy Ramesh +1 more 2024-09-10
11863183 Low power non-linear polar material based threshold logic gate multiplier Sasikanth Manipatruni, Yuan-Sheng Fang, Rajeev Kumar Dokania, Gaurav Thareja, Ramamoorthy Ramesh +1 more 2024-01-02
11764790 Majority logic gate having paraelectric input capacitors coupled to a conditioning scheme Rajeev Kumar Dokania, Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Ramamoorthy Ramesh +1 more 2023-09-19
11742860 Fabrication of a majority logic gate having non-linear input capacitors Sasikanth Manipatruni, Rafael Rios, Neal Reynolds, Ikenna Odinaka, Rajeev Kumar Dokania +2 more 2023-08-29
11711083 Majority gate based low power ferroelectric based adder with reset mechanism Sasikanth Manipatruni, Yuan-Sheng Fang, Rajeev Kumar Dokania, Guarav Thareja, Ramamoorthy Ramesh +1 more 2023-07-25
11705906 Majority logic gate having ferroelectric input capacitors and a pulsing scheme coupled to a conditioning logic Rajeev Kumar Dokania, Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Ramamoorthy Ramesh +1 more 2023-07-18
11616507 Ferroelectric based latch Sasikanth Manipatruni, Yuan-Sheng Fang, Rajeev Kumar Dokania, Ramamoorthy Ramesh, Amrita Mathuriya 2023-03-28
11539368 Majority logic gate with input paraelectric capacitors Sasikanth Manipatruni, Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Ramamoorthy Ramesh +1 more 2022-12-27
11502691 Method for using and forming low power ferroelectric based majority logic gate adder Sasikanth Manipatruni, Yuan-Sheng Fang, Rajeev Kumar Dokania, Gaurav Thareja, Ramamoorthy Ramesh +1 more 2022-11-15
11451232 Majority logic gate based flip-flop with non-linear polar material Sasikanth Manipatruni, Yuan-Sheng Fang, Rajeev Kumar Dokania, Ramamoorthy Ramesh, Amrita Mathuriya 2022-09-20
11418197 Majority logic gate having paraelectric input capacitors and a local conditioning mechanism Rajeev Kumar Dokania, Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Ramamoorthy Ramesh +1 more 2022-08-16
11394387 2-input NAND gate with non-linear input capacitors Sasikanth Manipatruni, Rafael Rios, Neal Reynolds, Ikenna Odinaka, Rajeev Kumar Dokania +2 more 2022-07-19
11381244 Low power ferroelectric based majority logic gate multiplier Sasikanth Manipatruni, Yuan-Sheng Fang, Rajeev Kumar Dokania, Gaurav Thareja, Ramamoorthy Ramesh +1 more 2022-07-05
11374574 Linear input and non-linear output threshold logic gate Sasikanth Manipatruni, Yuan-Sheng Fang, Rajeev Kumar Dokania, Gaurav Thareja, Ramamoorthy Ramesh +1 more 2022-06-28
11374575 Majority logic gate with non-linear input capacitors and conditioning logic Rajeev Kumar Dokania, Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Ramamoorthy Ramesh +1 more 2022-06-28
11296708 Low power ferroelectric based majority logic gate adder Sasikanth Manipatruni, Yuan-Sheng Fang, Rajeev Kumar Dokania, Gaurav Thareja, Ramamoorthy Ramesh +1 more 2022-04-05
11290112 Majority logic gate based XOR logic gate with non-linear input capacitors Sasikanth Manipatruni, Rafael Rios, Neal Reynolds, Ikenna Odinaka, Rajeev Kumar Dokania +2 more 2022-03-29
11290111 Majority logic gate based and-or-invert logic gate with non-linear input capacitors Sasikanth Manipatruni, Rafael Rios, Neal Reynolds, Ikenna Odinaka, Rajeev Kumar Dokania +2 more 2022-03-29
11283453 Low power ferroelectric based majority logic gate carry propagate and serial adder Sasikanth Manipatruni, Yuan-Sheng Fang, Rajeev Kumar Dokania, Gaurav Thareja, Ramamoorthy Ramesh +1 more 2022-03-22
11277137 Majority logic gate with non-linear input capacitors Sasikanth Manipatruni, Rafael Rios, Neal Reynolds, Ikenna Odinaka, Rajeev Kumar Dokania +2 more 2022-03-15
11165430 Majority logic gate based sequential circuit Sasikanth Manipatruni, Yuan-Sheng Fang, Rajeev Kumar Dokania, Gaurav Thareja, Ramamoorthy Ramesh +1 more 2021-11-02
11025254 Linear input and non-linear output threshold logic gate Sasikanth Manipatruni, Yuan-Sheng Fang, Rajeev Kumar Dokania, Gaurav Thareja, Ramamoorthy Ramesh +1 more 2021-06-01