Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12411657 | Asynchronous full-adder with majority or minority gates to generate carry-out true output | Amrita Mathuriya, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2025-09-09 |
| 12405768 | Asynchronous full-adder with majority or minority gates to generate carry-out false output | Amrita Mathuriya, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2025-09-02 |
| 12379898 | Asynchronous full-adder with majority or minority gates to generate sum false output | Amrita Mathuriya, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2025-08-05 |
| D1054360 | Interceptor blade | Nicholas J. Troche, Brian Steele | 2024-12-17 |
| 12015402 | Asynchronous consensus circuit with stacked ferroelectric non-planar capacitors | Amrita Mathuriya, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2024-06-18 |
| 12009820 | Asynchronous consensus circuit with majority gate based on non-linear capacitors | Amrita Mathuriya, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2024-06-11 |
| 11979148 | Asynchronous consensus circuit with stacked linear or paraelectric planar capacitors | Amrita Mathuriya, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2024-05-07 |
| 11909391 | Asynchronous completion tree circuit using multi-function threshold gate with input based adaptive threshold | Amrita Mathuriya, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2024-02-20 |
| 11901891 | Asynchronous consensus circuit with stacked ferroelectric planar capacitors | Amrita Mathuriya, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2024-02-13 |
| D1009803 | Cable guide | Nicholas J. Troche, Robert Barry | 2024-01-02 |
| 11863184 | Asynchronous validity tree circuit using multi-function threshold gate with input based adaptive threshold | Amrita Mathuriya, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2024-01-02 |
| 11855626 | Asynchronous consensus circuit with stacked linear or paraelectric non-planar capacitors | Amrita Mathuriya, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2023-12-26 |
| 11855627 | Asynchronous consensus circuit using multi-function threshold gate with input based adaptive threshold | Amrita Mathuriya, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2023-12-26 |
| 11817859 | Asynchronous circuit with multi-input threshold gate logic and 1-input threshold gate | Sasikanth Manipatruni, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya | 2023-11-14 |
| 11716083 | Asynchronous circuit with threshold logic | Sasikanth Manipatruni, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya | 2023-08-01 |
| 11716084 | Pull-up and pull-down networks controlled asynchronously by majority gate or minority gate logic | Sasikanth Manipatruni, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya | 2023-08-01 |
| 11716085 | Pull-up and pull-down networks controlled asynchronously by threshold gate logic | Sasikanth Manipatruni, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya | 2023-08-01 |
| 11716086 | Asynchronous circuit with majority gate or minority gate logic and 1-input threshold gate | Sasikanth Manipatruni, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya | 2023-08-01 |
| 11658664 | Asynchronous circuit with majority gate or minority gate logic | Sasikanth Manipatruni, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya | 2023-05-23 |
| 11652487 | Parallel pull-up and pull-down networks controlled asynchronously by majority gate or minority gate logic | Sasikanth Manipatruni, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya | 2023-05-16 |
| 11652482 | Parallel pull-up and pull-down networks controlled asynchronously by threshold logic gate | Sasikanth Manipatruni, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya | 2023-05-16 |
| 10885425 | Network traversal using neuromorphic instantiations of spike-time-dependent plasticity | Narayan Srinivasa | 2021-01-05 |
| 10846590 | Autonomous navigation using spiking neuromorphic computers | Narayan Srinivasa | 2020-11-24 |
| 10538160 | Combined power take-off and synchronizer assembly | Brian L. Rang, John M. Loeffler | 2020-01-21 |
| 9453566 | Hydromechanical transmission with double sump gear unit housing | John M. Loeffler, Daniel Paisley, Matthew James Rommel | 2016-09-27 |