Issued Patents All Time
Showing 26–50 of 72 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11967954 | Majority or minority logic gate with non-linear input capacitors without reset | Amrita Mathuriya, Rafael Rios, Darshak Doshi, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2024-04-23 |
| 11922105 | Computer-aided design tool for minimum gate count initialization | Sasikanth Manipatruni, Darshak Doshi, Rajeev Kumar Dokania, Amrita Mathuriya | 2024-03-05 |
| 11909391 | Asynchronous completion tree circuit using multi-function threshold gate with input based adaptive threshold | Amrita Mathuriya, Nabil Imam, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2024-02-20 |
| 11901891 | Asynchronous consensus circuit with stacked ferroelectric planar capacitors | Amrita Mathuriya, Nabil Imam, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2024-02-13 |
| 11888479 | Non-linear polar material based low power multiplier with NOR and NAND gate based reset mechanism | Amrita Mathuriya, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2024-01-30 |
| 11863184 | Asynchronous validity tree circuit using multi-function threshold gate with input based adaptive threshold | Amrita Mathuriya, Nabil Imam, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2024-01-02 |
| 11861279 | Computer-aided design tool for inverter minimization | Sasikanth Manipatruni, Darshak Doshi, Rajeev Kumar Dokania, Amrita Mathuriya | 2024-01-02 |
| 11861278 | Computer-aided design tool for gate pruning | Sasikanth Manipatruni, Darshak Doshi, Rajeev Kumar Dokania, Amrita Mathuriya | 2024-01-02 |
| 11855627 | Asynchronous consensus circuit using multi-function threshold gate with input based adaptive threshold | Amrita Mathuriya, Nabil Imam, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2023-12-26 |
| 11855626 | Asynchronous consensus circuit with stacked linear or paraelectric non-planar capacitors | Amrita Mathuriya, Nabil Imam, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2023-12-26 |
| 11853666 | Computer-aided design tool for wide-input logic initialization | Sasikanth Manipatruni, Darshak Doshi, Rajeev Kumar Dokania, Amrita Mathuriya | 2023-12-26 |
| 11817859 | Asynchronous circuit with multi-input threshold gate logic and 1-input threshold gate | Sasikanth Manipatruni, Nabil Imam, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya | 2023-11-14 |
| 11816408 | Computer-aided design tool for majority or minority inverter graph synthesis | Sasikanth Manipatruni, Darshak Doshi, Rajeev Kumar Dokania, Amrita Mathuriya | 2023-11-14 |
| 11809801 | Computer-aided design tool for circuit logic initialization | Sasikanth Manipatruni, Darshak Doshi, Rajeev Kumar Dokania, Amrita Mathuriya | 2023-11-07 |
| 11777504 | Non-linear polar material based latch | Amrita Mathuriya, Rajeev Kumar Dokania, Rafael Rios, Sasikanth Manipatruni | 2023-10-03 |
| 11764790 | Majority logic gate having paraelectric input capacitors coupled to a conditioning scheme | Rajeev Kumar Dokania, Amrita Mathuriya, Rafael Rios, Robert Menezes, Ramamoorthy Ramesh +1 more | 2023-09-19 |
| 11757452 | OR-and-invert logic based on a mix of majority or minority logic gate with non-linear input capacitors and other logic gates | Amrita Mathuriya, Rafael Rios, Darshak Doshi, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2023-09-12 |
| 11748537 | Computer-aided design tool for logic synthesis of a mix of CMOS gates and majority and minority logic circuits | Sasikanth Manipatruni, Darshak Doshi, Rajeev Kumar Dokania, Amrita Mathuriya | 2023-09-05 |
| 11750197 | AND-OR-invert logic based on a mix of majority OR minority logic gate with non-linear input capacitors and other logic gates | Amrita Mathuriya, Rafael Rios, Darshak Doshi, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2023-09-05 |
| 11742860 | Fabrication of a majority logic gate having non-linear input capacitors | Sasikanth Manipatruni, Rafael Rios, Neal Reynolds, Robert Menezes, Rajeev Kumar Dokania +2 more | 2023-08-29 |
| 11721690 | Method of adjusting threshold of a ferroelectric capacitive-input circuit | Amrita Mathuriya, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2023-08-08 |
| 11716086 | Asynchronous circuit with majority gate or minority gate logic and 1-input threshold gate | Sasikanth Manipatruni, Nabil Imam, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya | 2023-08-01 |
| 11716085 | Pull-up and pull-down networks controlled asynchronously by threshold gate logic | Sasikanth Manipatruni, Nabil Imam, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya | 2023-08-01 |
| 11716084 | Pull-up and pull-down networks controlled asynchronously by majority gate or minority gate logic | Sasikanth Manipatruni, Nabil Imam, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya | 2023-08-01 |
| 11716083 | Asynchronous circuit with threshold logic | Sasikanth Manipatruni, Nabil Imam, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya | 2023-08-01 |