Issued Patents All Time
Showing 25 most recent of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12336278 | Gate-all-around integrated circuit structures having high mobility | Rishabh Mehandru, Stephen M. Cea, Biswajeet Guha, Dax M. Crum, Tahir Ghani | 2025-06-17 |
| 12230687 | Lateral gate material arrangements for quantum dot devices | Stephanie A. Bojarski, Hubert C. George, Payam Amin, Patrick H. Keys, Ravi Pillarisetty +3 more | 2025-02-18 |
| 11922274 | Quantum dot devices with side and center screening gates | Hubert C. George, James S. Clarke, Ravi Pillarisetty, Brennen Mueller, Stephanie A. Bojarski +4 more | 2024-03-05 |
| 11677017 | Quantum well stacks for quantum dot devices | Ravi Pillarisetty, Van H. Le, Nicole K. Thomas, Hubert C. George, Jeanette M. Roberts +5 more | 2023-06-13 |
| 11581406 | Method of fabricating CMOS FinFETs by selectively etching a strained SiGe layer | Stephen M. Cea, Harold W. Kennel, Anand S. Murthy, Glenn A. Glass, Kelin J. Kuhn +1 more | 2023-02-14 |
| 11538806 | Gate-all-around integrated circuit structures having high mobility | Rishabh Mehandru, Stephen M. Cea, Biswajeet Guha, Dax M. Crum, Tahir Ghani | 2022-12-27 |
| 11387320 | Transistors with high concentration of germanium | Anand S. Murthy, Glenn A. Glass, Tahir Ghani, Ravi Pillarisetty, Niloy Mukherjee +3 more | 2022-07-12 |
| 11367722 | Stacked nanowire transistor structure with different channel geometries for stress | Aaron D. Lilak, Stephen M. Cea, Gilbert Dewey, Willy Rachmady, Rishabh Mehandru +4 more | 2022-06-21 |
| 11195919 | Method of fabricating a semiconductor device with strained SiGe fins and a Si cladding layer | Stephen M. Cea, Harold W. Kennel, Anand S. Murthy, Glenn A. Glass, Kelin J. Kuhn +1 more | 2021-12-07 |
| 11183564 | Quantum dot devices with strain control | Nicole K. Thomas, Ravi Pillarisetty, Payam Amin, Patrick H. Keys, Hubert C. George +7 more | 2021-11-23 |
| 11158731 | Quantum well stacks for quantum dot devices | Ravi Pillarisetty, Van H. Le, Nicole K. Thomas, Hubert C. George, Jeanette M. Roberts +5 more | 2021-10-26 |
| 11107891 | Hexagonal arrays for quantum dot devices | Ravi Pillarisetty, Hubert C. George, Nicole K. Thomas, Jeanette M. Roberts, Roman Caudillo +4 more | 2021-08-31 |
| 10868246 | Conductive bridge random access memory (CBRAM) devices with low thermal conductivity electrolyte sublayer | Elijah V. Karpov, Prashant Majhi, Jeffery D. Bielefeld | 2020-12-15 |
| 10854752 | High mobility strained channels for fin-based NMOS transistors | Stephen M. Cea, Harold W. Kennel, Glenn A. Glass, Anand S. Murthy, Willy Rachmady +1 more | 2020-12-01 |
| 10790281 | Stacked channel structures for MOSFETs | Rishabh Mehandru, Stephen M. Cea, Patrick H. Keys | 2020-09-29 |
| 10665770 | Fin strain in quantum dot devices | Ravi Pillarisetty, Kanwaljit Singh, Patrick H. Keys, Roman Caudillo, Hubert C. George +5 more | 2020-05-26 |
| 10600787 | Silicon PMOS with gallium nitride NMOS for voltage regulation | Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic, Peter G. Tolchinsky, Valluri Rao | 2020-03-24 |
| 10396211 | Functional metal oxide based microelectronic devices | Elijah V. Karpov, Prashant Majhi, Niloy Mukherjee, Charles C. Kuo, Uday Shah +2 more | 2019-08-27 |
| 10153372 | High mobility strained channels for fin-based NMOS transistors | Stephen M. Cea, Harold W. Kennel, Glenn A. Glass, Anand S. Murthy, Willy Rachmady +1 more | 2018-12-11 |
| 10128356 | P-tunneling field effect transistor device with pocket | Uygar E. Avci, Ian A. Young | 2018-11-13 |
| 10115822 | Methods of forming low band gap source and drain structures in microelectronic devices | Rafael Rios, Kelin J. Kuhn | 2018-10-30 |
| 10109711 | CMOS FinFET device having strained SiGe fins and a strained Si cladding layer on the NMOS channel | Stephen M. Cea, Harold W. Kennel, Anand S. Murthy, Glenn A. Glass, Kelin J. Kuhn +1 more | 2018-10-23 |
| 9972686 | Germanium tin channel transistors | Ravi Pillarisetty, Van H. Le, Willy Rachmady, Marko Radosavljevic, Han Wui Then +4 more | 2018-05-15 |
| 9935107 | CMOS FinFET device with dual strained cladding layers on relaxed SiGe fins, and method of fabricating the same | Stephen M. Cea, Harold W. Kennel, Kelin J. Kuhn, Tahir Ghani | 2018-04-03 |
| 9911835 | Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs | Stephen M. Cea, Gilbert Dewey, Benjamin Chu-Kung, Uygar E. Avci, Rafael Rios +4 more | 2018-03-06 |