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Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
WR

Willy Rachmady — 361 Patents

Intel: 347 patents #15 of 30,777Top 1%
Sony: 11 patents #4,056 of 25,231Top 20%
Google: 2 patents #10,599 of 22,993Top 50%
TRTahoe Research: 1 patents #81 of 215Top 40%
Beaverton, OR: #4 of 3,140 inventorsTop 1%
Oregon: #16 of 28,073 inventorsTop 1%
Overall (All Time): #835 of 4,157,543Top 1%
361 Patents All Time
Willy Rachmady has been granted 361 US patents while listed as an inventor at Intel. The first was granted in 2008 and the most recent in December 2025. Willy Rachmady ranks #835 of 4,157,543 US inventors in our database (top 0.02%). Patent records list Willy Rachmady in Beaverton, OR, US.

Patents per Year

Patents granted per year, 2008 to 2025Bar chart with a peak of 52 patents in 2022.peak 522008: 3 patents20082009: 3 patents2010: 13 patents20102011: 8 patents2012: 9 patents20122013: 9 patents2014: 15 patents20142015: 14 patents2016: 14 patents20162017: 22 patents2018: 19 patents20182019: 30 patents2020: 31 patents20202021: 33 patents2022: 52 patents20222023: 40 patents2024: 33 patents20242025: 13 patents2025

Issued Patents All Time

Showing 1–25 of 361 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12513958 Nanowire transistor fabrication with hardmask layers Seung Hoon Sung, Seok Hwan Kim, Kelin J. Kuhn, Jack T. Kavalieros 2025-12-30
12433007 Transistor gate trench engineering to decrease capacitance and resistance Seung Hoon Sung, Jack T. Kavalieros, Han Wui Then, Marko Radosavljevic 2025-09-30
12388011 Top gate recessed channel CMOS thin film transistor and methods of fabrication Gilbert Dewey, Ryan Keech, Cory Bomberger, Cheng-Ying Huang, Ashish Agrawal +1 more 2025-08-12
12369399 Gate-to-gate isolation for stacked transistor architecture via selective dielectric deposition structure Sudipto Naskar, Cheng-Ying Huang, Gilbert Dewey, Marko Radosavljevic, Nicole K. Thomas +2 more 2025-07-22
12363967 Integration methods to fabricate internal spacers for nanowire devices Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Anand S. Murthy, Mark Armstrong +2 more 2025-07-15
12342614 Asymmetric gate structures and contacts for stacked transistors Cheng-Ying Huang, Patrick Morrow, Arunshankar Venkataraman, Sean T. Ma, Nicole K. Thomas +2 more 2025-06-24
12288813 Gate-all-around integrated circuit structures having insulator fin on insulator substrate Aaron D. Lilak, Rishabh Mehandru, Cory E. Weber, Varun MISHRA 2025-04-29
12288807 Amorphization and regrowth of source-drain regions from the bottom-side of a semiconductor assembly Aaron D. Lilak, Rishabh Mehandru, Harold W. Kennel, Tahir Ghani 2025-04-29
12288803 Transistor with isolation below source and drain Cheng-Ying Huang, Matthew V. Metz, Nicholas G. Minutillo, Sean T. Ma, Anand S. Murthy +3 more 2025-04-29
12266570 Self-aligned interconnect structures and methods of fabrication Kimin Jun, Souvik Ghosh, Ashish Agrawal, Siddharth Chouksey, Jessica M. Torres +5 more 2025-04-01
12255137 Sideways vias in isolation areas to contact interior layers in stacked devices Ehren Mannebach, Aaron D. Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan +3 more 2025-03-18
12224202 Forming an oxide volume within a fin Cheng-Ying Huang, Gilbert Dewey, Jack T. Kavalieros, Aaron D. Lilak, Ehren Mannebach +3 more 2025-02-11
12199142 Neighboring gate-all-around integrated circuit structures having conductive contact stressor between epitaxial source or drain regions Siddharth Chouksey, Jack T. Kavalieros, Stephen M. Cea, Ashish Agrawal 2025-01-14
12183668 Thin-film transistors and MIM capacitors in exclusion zones Abhishek A. Sharma, Cheng-Ying Huang, Gilbert Dewey, Rajat K. Paul 2024-12-31 $16,542,000
12176408 Localized spacer for nanowire transistors and methods of fabrication Sudipto Naskar, Hsin-Fen Li, Christopher Parker, Prashant Wadhwa, Tahir Ghani +2 more 2024-12-24 $17,261,000
RE50222 Non-planar gate all-around device and method of fabrication thereof Ravi Pillarisetty, Van H. Le, Jack T. Kavaileros, Robert S. Chau, Jessica S. Kachian 2024-11-26
12148806 Stacked source-drain-gate connection and process for forming such Ehren Mannebach, Aaron D. Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan +2 more 2024-11-19 $25,575,000
12142634 Silicon and silicon germanium nanowire structures Kelin J. Kuhn, Seiyon Kim, Rafael Rios, Stephen M. Cea, Martin D. Giles +3 more 2024-11-12 $636,000
12107085 Interconnect techniques for electrically connecting source/drain regions of stacked transistors Aaron D. Lilak, Gilbert Dewey, Cheng-Ying Huang, Christopher J. Jezewski, Ehren Mannebach +4 more 2024-10-01 $20,560,000
12087750 Stacked-substrate FPGA semiconductor devices Abhishek A. Sharma, Ravi Pillarisetty, Gilbert Dewey, Jack T. Kavalieros 2024-09-10 $16,964,000
12080605 Backside contacts for semiconductor devices Aaron D. Lilak, Ehren Mannebach, Anh Phan, Richard E. Schenker, Stephanie A. Bojarski +4 more 2024-09-03 $14,017,000
12068319 High performance semiconductor oxide material channel regions for NMOS Gilbert Dewey, Jack T. Kavalieros, Cheng-Ying Huang, Matthew V. Metz, Sean T. Ma +3 more 2024-08-20 $20,163,000
12051723 PN-body-tied field effect transistors Aaron D. Lilak, Kerryann Marrietta Foley, Sayed Hasan, Patrick Morrow 2024-07-30 $27,313,000
12046637 Nanowire transistor fabrication with hardmask layers Seung Hoon Sung, Seiyon Kim, Kelin J. Kuhn, Jack T. Kavalieros 2024-07-23 $732,000
12033896 Isolation wall stressor structures to improve channel stress and their methods of fabrication Aaron D. Lilak, Christopher J. Jezewski, Rishabh Mehandru, Gilbert Dewey, Anh Phan 2024-07-09 $24,938,000