Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12342611 | Source or drain structures with vertical trenches | Ryan Keech, Anand S. Murthy, Aaron A. Budrevich, Peter Wells | 2025-06-24 |
| 12288808 | High aspect ratio source or drain structures with abrupt dopant profile | Ryan Keech, Anand S. Murthy, Suresh Vishwanath, Mohammad HASAN, Biswajeet Guha +1 more | 2025-04-29 |
| 12288803 | Transistor with isolation below source and drain | Willy Rachmady, Cheng-Ying Huang, Matthew V. Metz, Sean T. Ma, Anand S. Murthy +3 more | 2025-04-29 |
| 12224337 | PGaN enhancement mode HEMTs with dopant diffusion spacer | Michael Beumer, Robert Ehlert, Michael Robinson, Patrick Wallace, Peter Wells | 2025-02-11 |
| 12094881 | Arsenic-doped epitaxial source/drain regions for NMOS | Anand S. Murthy, Ryan Keech, Ritesh Jhaveri | 2024-09-17 |
| 11935887 | Source or drain structures with vertical trenches | Ryan Keech, Anand S. Murthy, Aaron A. Budrevich, Peter Wells | 2024-03-19 |
| 11923410 | Transistor with isolation below source and drain | Willy Rachmady, Cheng-Ying Huang, Matthew V. Metz, Sean T. Ma, Anand S. Murthy +3 more | 2024-03-05 |
| 11804523 | High aspect ratio source or drain structures with abrupt dopant profile | Ryan Keech, Anand S. Murthy, Suresh Vishwanath, Mohammad HASAN, Biswajeet Guha +1 more | 2023-10-31 |
| 11756998 | Source-channel junction for III-V metal-oxide-semiconductor field effect transistors (MOSFETs) | Cheng-Ying Huang, Tahir Ghani, Jack T. Kavalieros, Anand S. Murthy, Harold W. Kennel +4 more | 2023-09-12 |
| 11695081 | Channel layer formation for III-V metal-oxide-semiconductor field effect transistors (MOSFETs) | Sean T. Ma, Cheng-Ying Huang, Tahir Ghani, Jack T. Kavalieros, Anand S. Murthy +4 more | 2023-07-04 |
| 11610889 | Arsenic-doped epitaxial, source/drain regions for NMOS | Anand S. Murthy, Ryan Keech, Ritesh Jhaveri | 2023-03-21 |
| 11557658 | Transistors with high density channel semiconductor over dielectric material | Gilbert Dewey, Sean T. Ma, Tahir Ghani, Willy Rachmady, Cheng-Ying Huang +3 more | 2023-01-17 |
| 11552169 | Source or drain structures with phosphorous and arsenic co-dopants | Anand S. Murthy, Ryan Keech, Suresh Vishwanath | 2023-01-10 |
| 11508577 | Channel layer formation for III-V metal-oxide-semiconductor field effect transistors (MOSFETs) | Gilbert Dewey, Matthew V. Metz, Willy Rachmady, Sean T. Ma, Cheng-Ying Huang +4 more | 2022-11-22 |
| 11355621 | Non-planar semiconductor device including a replacement channel structure | Gilbert Dewey, Willy Rachmady, Sean T. Ma, Tahir Ghani, Matthew V. Metz +2 more | 2022-06-07 |
| 11276694 | Transistor structure with indium phosphide channel | Willy Rachmady, Matthew V. Metz, Gilbert Dewey, Cheng-Ying Huang, Jack T. Kavalieros +2 more | 2022-03-15 |
| 11257904 | Source-channel junction for III-V metal-oxide-semiconductor field effect transistors (MOSFETs) | Cheng-Ying Huang, Tahir Ghani, Jack T. Kavalieros, Anand S. Murthy, Harold W. Kennel +4 more | 2022-02-22 |
| 11171207 | Transistor with isolation below source and drain | Willy Rachmady, Cheng-Ying Huang, Matthew V. Metz, Sean T. Ma, Anand S. Murthy +3 more | 2021-11-09 |
| 11164974 | Channel layer formed in an art trench | Willy Rachmady, Matthew V. Metz, Gilbert Dewey, Nancy Zelick, Harold W. Kennel +1 more | 2021-11-02 |
| 11164747 | Group III-V semiconductor devices having asymmetric source and drain structures | Sean T. Ma, Gilbert Dewey, Willy Rachmady, Harold W. Kennel, Cheng-Ying Huang +3 more | 2021-11-02 |
| 11049773 | Art trench spacers to enable fin release for non-lattice matched channels | Gilbert Dewey, Matthew V. Metz, Sean T. Ma, Cheng-Ying Huang, Tahir Ghani +4 more | 2021-06-29 |