Issued Patents All Time
Showing 25 most recent of 88 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12414339 | Formation of gate spacers for strained PMOS gate-all-around transistor structures | Ashish Agrawal, Gilbert Dewey, Siddharth Chouksey, Jack T. Kavalieros | 2025-09-09 |
| 12388011 | Top gate recessed channel CMOS thin film transistor and methods of fabrication | Gilbert Dewey, Ryan Keech, Cory Bomberger, Ashish Agrawal, Willy Rachmady +1 more | 2025-08-12 |
| 12369399 | Gate-to-gate isolation for stacked transistor architecture via selective dielectric deposition structure | Willy Rachmady, Sudipto Naskar, Gilbert Dewey, Marko Radosavljevic, Nicole K. Thomas +2 more | 2025-07-22 |
| 12342614 | Asymmetric gate structures and contacts for stacked transistors | Patrick Morrow, Arunshankar Venkataraman, Sean T. Ma, Willy Rachmady, Nicole K. Thomas +2 more | 2025-06-24 |
| 12288803 | Transistor with isolation below source and drain | Willy Rachmady, Matthew V. Metz, Nicholas G. Minutillo, Sean T. Ma, Anand S. Murthy +3 more | 2025-04-29 |
| 12255137 | Sideways vias in isolation areas to contact interior layers in stacked devices | Ehren Mannebach, Aaron D. Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan +3 more | 2025-03-18 |
| 12243875 | Forksheet transistors with dielectric or conductive spine | Seung Hoon Sung, Marko Radosavljevic, Christopher M. Neumann, Susmita Ghose, Varun MISHRA +4 more | 2025-03-04 |
| 12230635 | Gate-all-around integrated circuit structures having depopulated channel structures using selective bottom-up approach | Nicole K. Thomas, Ehren Mannebach, Marko Radosavljevic | 2025-02-18 |
| 12224202 | Forming an oxide volume within a fin | Gilbert Dewey, Jack T. Kavalieros, Aaron D. Lilak, Ehren Mannebach, Patrick Morrow +3 more | 2025-02-11 |
| 12183668 | Thin-film transistors and MIM capacitors in exclusion zones | Abhishek A. Sharma, Willy Rachmady, Gilbert Dewey, Rajat K. Paul | 2024-12-31 |
| 12148806 | Stacked source-drain-gate connection and process for forming such | Ehren Mannebach, Aaron D. Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan +2 more | 2024-11-19 |
| 12120865 | Arrays of double-sided dram cells including capacitors on the frontside and backside of a stacked transistor structure | Ashish Agrawal, Gilbert Dewey, Abhishek A. Sharma, Wilfred Gomes, Jack T. Kavalieros | 2024-10-15 |
| 12107085 | Interconnect techniques for electrically connecting source/drain regions of stacked transistors | Aaron D. Lilak, Gilbert Dewey, Christopher J. Jezewski, Ehren Mannebach, Rishabh Mehandru +4 more | 2024-10-01 |
| 12068319 | High performance semiconductor oxide material channel regions for NMOS | Gilbert Dewey, Willy Rachmady, Jack T. Kavalieros, Matthew V. Metz, Sean T. Ma +3 more | 2024-08-20 |
| 12020929 | Epitaxial layer with substantially parallel sides | Gilbert Dewey, Jack T. Kavalieros, Aaron D. Lilak, Ehren Mannebach, Patrick Morrow +3 more | 2024-06-25 |
| 11996411 | Stacked forksheet transistors | Gilbert Dewey, Anh Phan, Nicole K. Thomas, Urusa Alaan, Seung Hoon Sung +8 more | 2024-05-28 |
| 11996408 | Leave-behind protective layer having secondary purpose | Aaron D. Lilak, Anh Phan, Ehren Mannebach, Stephanie A. Bojarski, Gilbert Dewey +2 more | 2024-05-28 |
| 11996404 | Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material | Gilbert Dewey, Ashish Agrawal, Kimin Jun, Willy Rachmady, Zachary Geiger +5 more | 2024-05-28 |
| 11942416 | Sideways vias in isolation areas to contact interior layers in stacked devices | Ehren Mannebach, Aaron D. Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan +3 more | 2024-03-26 |
| 11935891 | Non-silicon N-type and P-type stacked transistors for integrated circuit devices | Gilbert Dewey, Patrick Morrow, Ravi Pillarisetty, Rishabh Mehandru, Willy Rachmady +1 more | 2024-03-19 |
| 11929435 | Ferroelectric gate stack for band-to-band tunneling reduction | Gilbert Dewey, Willy Rachmady, Jack T. Kavalieros, Matthew V. Metz, Sean T. Ma +2 more | 2024-03-12 |
| 11929320 | Top gate recessed channel CMOS thin film transistor in the back end of line and methods of fabrication | Gilbert Dewey, Ryan Keech, Cory Bomberger, Ashish Agrawal, Willy Rachmady +1 more | 2024-03-12 |
| 11923410 | Transistor with isolation below source and drain | Willy Rachmady, Matthew V. Metz, Nicholas G. Minutillo, Sean T. Ma, Anand S. Murthy +3 more | 2024-03-05 |
| 11923370 | Forksheet transistors with dielectric or conductive spine | Seung Hoon Sung, Marko Radosavljevic, Christopher M. Neumann, Susmita Ghose, Varun MISHRA +4 more | 2024-03-05 |
| 11916118 | Stacked source-drain-gate connection and process for forming such | Ehren Mannebach, Aaron D. Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan +2 more | 2024-02-27 |